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#26 GenerateTilelink now report tilelink source ID Scala CI #390: Commit 2cd18f9 pushed by Dolu1990
September 20, 2024 20:12 3m 28s dev
dev
September 20, 2024 20:12 3m 28s
#26 add --tl-sink-width=Int Scala CI #389: Commit bd36a07 pushed by Dolu1990
September 20, 2024 16:23 3m 49s dev
dev
September 20, 2024 16:23 3m 49s
#26 fix false xprop Scala CI #388: Commit 25ac30e pushed by Dolu1990
September 20, 2024 12:53 3m 38s dev
dev
September 20, 2024 12:53 3m 38s
Got the FPU to work in mixed modes (XLEN != FLEN) Scala CI #387: Commit ccb0e1d pushed by Dolu1990
September 19, 2024 15:49 3m 24s dev
dev
September 19, 2024 15:49 3m 24s
fix build.sbt Scala CI #386: Commit 8abcd9b pushed by Dolu1990
September 19, 2024 14:19 7m 2s dev
dev
September 19, 2024 14:19 7m 2s
#26 WhiteboxerPlugin can provide probes as outputs via --with-whitebo… Scala CI #385: Commit 6a8a6b6 pushed by Dolu1990
September 17, 2024 10:58 3m 31s dev
dev
September 17, 2024 10:58 3m 31s
#26 add --with-hart-id-input Scala CI #384: Commit 2d612c0 pushed by Dolu1990
September 14, 2024 15:34 3m 43s dev
dev
September 14, 2024 15:34 3m 43s
cleaning Scala CI #383: Commit e31ccac pushed by Dolu1990
September 14, 2024 15:13 3m 18s dev
dev
September 14, 2024 15:13 3m 18s
#26 fix generate tilelink PMA Scala CI #382: Commit 061a9b5 pushed by Dolu1990
September 14, 2024 14:54 3m 21s dev
dev
September 14, 2024 14:54 3m 21s
#26 add GenerateTilelink Scala CI #381: Commit 6263911 pushed by Dolu1990
September 14, 2024 13:54 3m 20s dev
dev
September 14, 2024 13:54 3m 20s
Fix TlTestbench Scala CI #380: Commit 5a04456 pushed by Dolu1990
September 14, 2024 13:30 3m 30s dev
dev
September 14, 2024 13:30 3m 30s
Relax TrapPlugin commit timings Scala CI #379: Commit 74ae80e pushed by Dolu1990
September 11, 2024 14:00 3m 24s dev
dev
September 11, 2024 14:00 3m 24s
sync Scala CI #378: Commit 9228641 pushed by Dolu1990
September 11, 2024 12:49 3m 56s dev
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September 11, 2024 12:49 3m 56s
Improve FPU flags timings Scala CI #377: Commit e30fe27 pushed by Dolu1990
September 11, 2024 12:48 3m 41s dev
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September 11, 2024 12:48 3m 41s
sync Scala CI #376: Commit 8bea734 pushed by Dolu1990
September 10, 2024 15:41 3m 37s dev
dev
September 10, 2024 15:41 3m 37s
sync Scala CI #375: Commit 78b75ee pushed by Dolu1990
September 10, 2024 09:10 3m 23s dev
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September 10, 2024 09:10 3m 23s
Add --relaxed-mul-inputs Scala CI #374: Commit 4f36be2 pushed by Dolu1990
September 9, 2024 10:32 3m 31s dev
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September 9, 2024 10:32 3m 31s
sync Scala CI #373: Commit c2ff814 pushed by Dolu1990
September 9, 2024 08:59 3m 49s dev
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September 9, 2024 08:59 3m 49s
workaround lsuPlugin storeRs2At bad fpu scheduling Scala CI #372: Commit a3fe8c3 pushed by Dolu1990
September 7, 2024 09:35 3m 26s dev
dev
September 7, 2024 09:35 3m 26s
Litex SOC now avoid using ram with byte mask in the L2 cache Scala CI #371: Commit e7c9f4a pushed by Dolu1990
September 6, 2024 14:04 3m 26s dev
dev
September 6, 2024 14:04 3m 26s
sync Scala CI #370: Commit a15ea92 pushed by Dolu1990
September 5, 2024 11:14 3m 31s dev
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September 5, 2024 11:14 3m 31s
#23 readme++ Scala CI #369: Commit 4195c2a pushed by Dolu1990
September 4, 2024 10:50 4m 6s dev
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September 4, 2024 10:50 4m 6s
sync Scala CI #368: Commit c99ad0d pushed by Dolu1990
September 4, 2024 06:11 3m 39s dev
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September 4, 2024 06:11 3m 39s
Fix FpuPackerPlugin linkedHashMap.keys.map not being linked anymore XD Scala CI #367: Commit ba69a8a pushed by Dolu1990
September 4, 2024 05:35 3m 25s dev
dev
September 4, 2024 05:35 3m 25s
Litex soc withLowLatencyPeriph added Scala CI #366: Commit 63933cd pushed by Dolu1990
September 3, 2024 14:33 3m 21s dev
dev
September 3, 2024 14:33 3m 21s