Add --relaxed-mul-inputs

SpinalHDL · Sep 9, 2024 · 4f36be2 · 4f36be2
1 parent c2ff814
commit 4f36be2
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Showing 3 changed files with 18 additions and 9 deletions.
diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala
@@ -107,6 +107,7 @@ class ParamSimple(){
   var relaxedSrc = true
   var relaxedBtb = false
   var relaxedDiv = false
+  var relaxedMulInputs = false
   var allowBypassFrom = 100 //100 => disabled
   var additionalPerformanceCounters = 0
   var withPerformanceCounters = false
@@ -343,6 +344,7 @@ class ParamSimple(){
     opt[Int]("dispatcher-at") action { (v, c) => dispatcherAt = v }
     opt[Long]("reset-vector") unbounded() action { (v, c) => resetVector = v }
     opt[Unit]("relaxed-div") action { (v, c) => relaxedDiv = true }
+    opt[Unit]("relaxed-mul-inputs") action { (v, c) => relaxedMulInputs = true }
     opt[Unit]("relaxed-branch") action { (v, c) => relaxedBranch = true }
     opt[Unit]("relaxed-shift") action { (v, c) => relaxedShift = true }
     opt[Unit]("relaxed-src") action { (v, c) => relaxedSrc = true }
@@ -669,7 +671,7 @@ class ParamSimple(){
     }
 
     if(withMul) {
-      plugins += new MulPlugin(early0, keepMulSrc = mulKeepSrc)
+      plugins += new MulPlugin(early0, keepMulSrc = mulKeepSrc, mulAt = relaxedMulInputs.toInt)
     }
     if(withDiv) {
       plugins += new RsUnsignedPlugin("lane0")

diff --git a/src/main/scala/vexiiriscv/execute/MulPlugin.scala b/src/main/scala/vexiiriscv/execute/MulPlugin.scala
@@ -39,8 +39,14 @@ class MulPlugin(val layer : LaneLayer,
 
 
   override def inject(src1: Bits, src2: Bits): Unit = {
-    logic.src(logic.keys.MUL_SRC1) := src1
-    logic.src(logic.keys.MUL_SRC2) := src2
+    cmdAt match {
+      case 0 =>
+        logic.src(logic.keys.MUL_SRC1) := src1
+        logic.src(logic.keys.MUL_SRC2) := src2
+      case -1 =>
+        logic.mul.bypass(logic.keys.MUL_SRC1) := src1
+        logic.mul.bypass(logic.keys.MUL_SRC2) := src2
+    }
   }
 
   override def rspAt: Int = writebackAt
@@ -51,7 +57,7 @@ class MulPlugin(val layer : LaneLayer,
     awaitBuild()
     import SrcKeys._
 
-    if (bufferedHigh == None) bufferedHigh = Some(Riscv.XLEN >= 64)
+    if (bufferedHigh == None) bufferedHigh = Some(Riscv.XLEN >= 64 || mulAt > 0)
     if (bufferedHigh.get) {
       el.setDecodingDefault(HIGH, False)
     }
@@ -91,8 +97,9 @@ class MulPlugin(val layer : LaneLayer,
     import keys._
 
     val src = new el.Execute(cmdAt) {
-      val rs1 = up(el(IntRegFile, RS1))
-      val rs2 = up(el(IntRegFile, RS2))
+      val node = (cmdAt == -1).mux(down, up)
+      val rs1 = node(el(IntRegFile, RS1))
+      val rs2 = node(el(IntRegFile, RS2))
       useRsUnsignedPlugin match {
         case false => {
           MUL_SRC1 := (RS1_SIGNED && rs1.msb) ## (rs1)

diff --git a/src/main/scala/vexiiriscv/execute/fpu/PipelinedMul.scala b/src/main/scala/vexiiriscv/execute/fpu/PipelinedMul.scala
@@ -40,16 +40,16 @@ class PipelinedMul(rsA : Stageable[UInt],
   val mul = new Area{
     import mulStage._
     splits.foreach(e => MUL_SLICES1(e.id) := (rsA(e.offsetA, e.widthA bits) * rsB(e.offsetB, e.widthB bits)))
-    KeepAttribute(mulStage(rsA))
-    KeepAttribute(mulStage(rsB))
+//    KeepAttribute(mulStage(rsA))
+//    KeepAttribute(mulStage(rsB))
   }
 
   val sum1 = new Area {
     import sum1Stage._
     MUL_SUM1 := (if(sum1Takes != 0) splits.take(sum1Takes).map(e => (MUL_SLICES1(e.id) << e.offsetC).resize(finalWidth)).reduceBalancedTree(_ + _).resized else U(0))
     sum1Stage(MUL_SLICES2) := Vec(MUL_SLICES1.drop(sum1Takes))
 
-    KeepAttribute(sum1Stage(MUL_SLICES2))
+//    KeepAttribute(sum1Stage(MUL_SLICES2))
   }
 
   val sum2 = new Area {