#26 GenerateTilelink now report tilelink source ID

SpinalHDL · Sep 20, 2024 · 2cd18f9 · 2cd18f9
1 parent bd36a07
commit 2cd18f9
Show file tree

Hide file tree

Showing 3 changed files with 11 additions and 3 deletions.
diff --git a/ext/SpinalHDL b/ext/SpinalHDL
diff --git a/src/main/scala/vexiiriscv/Generate.scala b/src/main/scala/vexiiriscv/Generate.scala
@@ -108,6 +108,13 @@ object GenerateTilelink extends App {
       }
     }
   }
+
+  for(m <- report.toplevel.mem.node.m2s.parameters.masters){
+    println(m.name)
+    for(source <- m.mapping){
+      println(s"- ${source.id} ${source.emits}")
+    }
+  }
 }
 
 

diff --git a/src/main/scala/vexiiriscv/fetch/FetchL1Bus.scala b/src/main/scala/vexiiriscv/fetch/FetchL1Bus.scala
@@ -42,7 +42,8 @@ case class FetchL1BusParam(physicalWidth : Int,
       addressWidth = physicalWidth,
       dataWidth = dataWidth,
       transfers = tilelink.M2sTransfers(get = SizeRange(lineSize))
-    )
+    ),
+    name = name
   )
 }
 
@@ -163,7 +164,7 @@ case class FetchL1Bus(p : FetchL1BusParam) extends Bundle with IMasterSlave {
   }.bmb
 
   def toTilelink(): tilelink.Bus = new Composite(this, "toTilelink"){
-    val bus = tilelink.Bus(p.toTileLinkM2sParameters(null))
+    val bus = tilelink.Bus(p.toTileLinkM2sParameters(FetchL1Bus.this))
     bus.a.valid := cmd.valid
     bus.a.opcode  := tilelink.Opcode.A.GET
     bus.a.param   := 0