#26 WhiteboxerPlugin can provide probes as outputs via --with-whitebo…

…xer-outputs

Add WhiteboxerPlugin_logic_commits_xxx to trace commits activity easily

src/main/scala/vexiiriscv/Param.scala

@@ -102,6 +102,7 @@ class ParamSimple(){
   var fpuIgnoreSubnormal = false
   var withRvd = false
   var withRvZb = false
+  var withWhiteboxerOutputs = false
   var privParam = PrivilegedParam.base
   var lsuForkAt = 0
   var lsuPmaAt = 0
@@ -225,7 +226,7 @@ class ParamSimple(){
     lsuL1Ways = 4
     lsuL1RefillCount = 8
     lsuL1WritebackCount = 8
-//    lsuL1Coherency = true
+    lsuL1Coherency = true
 //    lsuStoreBufferSlots = 2
 //    lsuStoreBufferOps = 32
     lsuStoreBufferSlots = 4
@@ -462,6 +463,7 @@ class ParamSimple(){
     opt[Unit]("with-rvd") action { (v, c) => withRvd = true; withRvf = true }
     opt[Unit]("with-rvc") action { (v, c) => withRvc = true; withAlignerBuffer = true }
     opt[Unit]("with-rvZb") action { (v, c) => withRvZb = true }
+    opt[Unit]("with-whiteboxer-outputs") action { (v, c) => withWhiteboxerOutputs = true }
     opt[Unit]("with-hart-id-input") action { (v, c) => withHartIdInput = true }
     opt[Unit]("fma-reduced-accuracy") action { (v, c) => fpuFmaFullAccuracy = false }
     opt[Unit]("fpu-ignore-subnormal") action { (v, c) => fpuIgnoreSubnormal = true }
@@ -840,7 +842,9 @@ class ParamSimple(){
       //      plugins += new execute.fpu.FpuEmbedded()
     }
 
-    plugins += new WhiteboxerPlugin()
+    plugins += new WhiteboxerPlugin(
+      withOutputs = withWhiteboxerOutputs
+    )
   }
 }
 

src/main/scala/vexiiriscv/misc/TrapPlugin.scala

@@ -95,7 +95,7 @@ object TrapArg{
 
 
 //TODO ensure that CSR stored in ram are properly masked on read (mtval ... )
-class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
+class TrapPlugin(val trapAt : Int) extends FiberPlugin with TrapService {
   override def trapHandelingAt: Int = trapAt
 
   def askWake(hartId : Int) = api.harts(hartId).askWake := True

src/main/scala/vexiiriscv/soc/litex/Soc.scala

@@ -459,6 +459,9 @@ object SocGen extends App{
 //  val to = cpu0.reflectBaseType("CsrAccessPlugin_bus_write_halt")
 //  val to = cpu0.reflectBaseType("FpuCsrPlugin_api_flags_NX")
 
+//  val from = cpu0.reflectBaseType("LsuL1Plugin_logic_c_pip_ctrl_2_up_onPreCtrl_HIT_DIRTY") //That big
+//  val to = cpu0.reflectBaseType("PrivilegedPlugin_logic_harts_0_debug_dcsr_stepLogic_stepped")
+
 
 
 //  val drivers = mutable.LinkedHashSet[BaseType]()

src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala

@@ -5,7 +5,7 @@ import spinal.core.sim._
 import spinal.lib._
 import spinal.lib.misc.plugin.FiberPlugin
 import vexiiriscv.Global
-import vexiiriscv.Global.{HART_COUNT, TRAP}
+import vexiiriscv.Global.{COMMIT, HART_COUNT, TRAP}
 import vexiiriscv.decode.{Decode, DecodePipelinePlugin, DecoderPlugin}
 import vexiiriscv.execute._
 import vexiiriscv.execute.lsu._
@@ -18,15 +18,19 @@ import vexiiriscv.schedule.{DispatchPlugin, FlushCmd, ReschedulePlugin}
 
 import scala.collection.mutable.ArrayBuffer
 
-class WhiteboxerPlugin extends FiberPlugin{
+class WhiteboxerPlugin(withOutputs : Boolean) extends FiberPlugin{
 
   val logic = during setup new Logic()
   class Logic extends Area{
     val pbp = host[PipelineBuilderPlugin]
     val buildBefore = retains(pbp.elaborationLock)
     awaitBuild()
 
-    def wrap[T <: Data](that: T): T = CombInit(that).simPublic
+    def wrap[T <: Data](that: T): T = {
+      val buffered = CombInit(that).simPublic
+      if(withOutputs) out(buffered)
+      buffered
+    }
 
     val fpp = host[FetchPipelinePlugin]
     val dpp = host[DecodePipelinePlugin]
@@ -105,6 +109,23 @@ class WhiteboxerPlugin extends FiberPlugin{
       val ports = host.list[CompletionService].flatMap(cp => cp.getCompletions().map(wrap))
     }
 
+    val commits = new Area {
+      var lanes = host.list[ExecuteLaneService]
+      val trapAt = host[TrapPlugin].trapAt
+      val ctrls = lanes.map(_.execute(trapAt))
+      case class Commits() extends Bundle{
+        val pc = Global.PC()
+        val age = Execute.LANE_AGE()
+      }
+      val ports = for(i <- 0 until ctrls.size) yield new Area{
+        val oh = ctrls.map(ctrl => ctrl.down.isFiring && ctrl.down(COMMIT) && ctrl.down(Execute.LANE_AGE) === i)
+        val reader = ctrls.reader(oh)
+        val valid = wrap(oh.orR)
+        val pc = wrap(reader(_(Global.PC)))
+        val uop = wrap(reader(_(Decode.UOP)))
+      }
+    }
+
     val reschedules = new Area {
       val rp = host[ReschedulePlugin]
       rp.elaborationLock.await()