Litex SOC now avoid using ram with byte mask in the L2 cache

SpinalHDL · Sep 6, 2024 · e7c9f4a · e7c9f4a
1 parent a15ea92
commit e7c9f4a
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/src/main/scala/vexiiriscv/soc/litex/Soc.scala b/src/main/scala/vexiiriscv/soc/litex/Soc.scala
@@ -306,6 +306,12 @@ class Soc(c : SocConfig) extends Component {
       ))
       if (c.withDma) Axi4SpecRenamer(dma.bus)
 
+      if(withCoherency && withL2){
+        for (bank <- splited.wc.l2.cache.logic.cache.cache.data.banks) {
+          bank.ram.preventAsBlackBox() // Some synthesis tools have issues inferring efficient layout when byte mask is used.
+        }
+      }
+
 
       println(MemoryConnection.getMemoryTransfers(vexiis(0).dBus))