Updates #105
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Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Use oh_verilog_define instead of oh_synthesis_options. The below commit introduced the CFG_PLATFORM variable which we now need to define in our FPGA projects. commit 998f302 Author: Andreas Olofsson <andreas@adapteva.com> Date: Wed Nov 22 11:32:20 2017 -0500 Fixed elink platform compile errors -Ultrascale changes broke the zynq design -Adding CFG_PLATFORM variable to control compilation target Signed-off-by: Ola Jeppsson <ola@adapteva.com>
|= operator is not supported. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Fix remaining issues for Zynq that were introduced by the Ultrascale+ implementation. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Missed this one in the previous commit.
This is in preparation of adding HDMI block designs for 7020 and 7010. For some reason Vivado automatically strips removes the offset during synthesis(?) which breaks the constraints.
Initial import from github.com/peteasa/parallella-fpga.git TODO: Need to add ADI IPs to the repository. Not tested.
Use parallella-fgpa version. IIRC oh master doesn't synthesize the headless block designs correctly. But the parallella-fpga project HDMI projects does work with parallella-base from oh. This is the most likely culprit I can come up with, but I haven't tested it yet.
Import: https://github.com/analogdevicesinc/hdl.git Branch: hdl_2018_r2 Commit: 28df7548b002cf7201ed291a85edfa7643b5f52b These directories preseved, the rest was pruned: . ├── library │ ├── altera │ │ └── common │ │ ├── alt_ifconv │ │ ├── alt_mem_asym │ │ ├── alt_mul │ │ └── alt_serdes │ ├── axi_clkgen │ │ └── bd │ ├── axi_hdmi_tx │ ├── axi_spdif_tx │ ├── common │ ├── scripts │ └── xilinx │ └── common └── projects └── scripts
Import from github.com/peteasa/parallella-fpga.git H/T @peteasa ! TODO: Not tested! Replace AXI_VDMA with axi_dmac from analogdevicesinc/hdl See this in analogdevices/hdl commit for info commit a0e3997687a32933c0bef3e255430199a5e8c3c1 Author: AndreiGrozav <andrei.grozav@analog.com> Date: Fri May 11 18:42:59 2018 +0300 common/zed_system_bd.tcl: Replace VDMA Replace Xilinx VDMA IP with ADI axi_dmac IP.
The reference ADI design changed from using axi_vdma to axi_dmac. Import axi_dmac directory from upstream analogdevicesinc/hdl hdl_2018_R2 branch. Commit: 28df7548b002cf7201ed291a85edfa7643b5f52b
We do the same thing as this commit in analogdevicesinc/hdl.git
commit a0e3997687a32933c0bef3e255430199a5e8c3c1
Author: AndreiGrozav <andrei.grozav@analog.com>
Date: Fri May 11 18:42:59 2018 +0300
common/zed_system_bd.tcl: Replace VDMA
Replace Xilinx VDMA IP with ADI axi_dmac IP.
Not tested.
Apparently axi_dmac uses more resources than axi_vdma did. Relax clk_wiz_0 (used by SPDIF) as much as possible. No buffers on input or output. Unfortunately implementation still errors out because of block-RAM over-utilization: Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device ERROR: [Place 30-640] Place Check : This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 121 of such cell types but only 120 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 43b4e0ea
There is not enough BRAM cells for the z7010 HDMI project.
Rename clk_wiz_0 to spdif_clk_0 for clarity. Use interface connection between axi_dmac_0/m_axis <--> axi_hdmi_tx_0/s_axis.
WARNING: [Vivado 12-2489] -period contains time 3.333333 which will be rounded to 3.333 to ensure it is an integer multiple of 1 picosecond [/home/olaj/Projects/Adapteva/oh/src/parallella/fpga/paral lella_timing.xdc:1]
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Headless tested and working.
HDMI bitstream video tested & working (need different device tree).
Sound not tested for HDMI design.