The Single Port Random Access Memory (RAM) project is a Verilog implementation of a simple RAM controller with single-port access. It provides basic functionality to read from and write to a memory array using address, write enable, and chip enable signals. The project is aimed at educational purposes and serves as a foundation for understanding memory controllers in digital design.

Features:

• Implements a single-port RAM controller module in Verilog.

• Supports read and write operations to the memory array.

• Provides synchronous operation with the clock signal for proper timing.

• Includes reset functionality to initialize the memory array during startup.

Project Structure:

• single_port_ram.v: Verilog module defining the single-port RAM controller.

• single_port_ram_tb.v: Test bench for simulating the single-port RAM controller.

• README.md: Project documentation including description, usage instructions, and pin table.

Pin Diagram-

Pin Table:-

• clk -> Clock input signal

• rst -> Reset input signal

• addr -> Address input signal

• we -> Write enable input signal

• ce -> Chip enable input signal

• data -> Bidirectional data input/output signal

Waveform:-