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GauravDhak/README.md 
**Hi there!** 👋 **I'm Gaurav Dhak**

Welcome to my GitHub profile! I'm a dedicated student at NIELIT Aurangabad, pursuing a B.Tech in Electronics System Engineering. Here, you'll find some of my projects and contributions related to electronics and VLSI. Feel free to explore and connect with me!

🌱 **Currently Learning**

- Embedded Systems
- Verilog
- Digital Frontend Design
- ASIC Design
- CMOS Technology

📫 **How to Reach Me**

- Email: gauravdhak2003@gmail.com

🔗 **Connect with Me**

[LinkedIn](https://www.linkedin.com/in/gauravdhak/)  
[Hashnode](https://gaurav789.hashnode.dev)  
[Twitter](https://twitter.com/GauravDhak)

🚀 **Skills**

**Languages:**
- C/C++
- Python
- Verilog HDL

**Tools & Technologies:**
- GNU/Linux
- Xilinx ISE
- FPGA Prototyping
- RTL Coding
- Linux OS

**Design and Development:**
- Very-Large-Scale Integration (VLSI)
- Application-Specific Integrated Circuits (ASIC)
- Verilog/SystemVerilog
- Universal Verification Methodology (UVM)
- RTL Design
- Static Timing Analysis (STA)
- Electronic Design Automation (EDA)


If you share similar interests or have something interesting to discuss, feel free to reach out!

Happy coding! 🚀

Popular repositories Loading

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    This repository is a comprehensive collection of resources aimed at helping software engineers and system architects enhance their skills in system design.

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  2. Single-port-Random-Access-Memory-RAM- Single-port-Random-Access-Memory-RAM- Public

    Single port Random Access Memory (RAM)" typically refers to a type of memory module or chip where data can be read from or written to through a single port, meaning it can handle one data access op…

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  3. LRU-Cache-Memory LRU-Cache-Memory Public

    An LRU (Least Recently Used) cache memory in Verilog is designed to store and manage frequently accessed data by implementing a replacement policy that evicts the least recently used entries, ensur…

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  4. 2-bit-Branch-Predictor-in-Verilog 2-bit-Branch-Predictor-in-Verilog Public

    This project implements a 2-bit branch predictor in Verilog. Branch prediction is a technique used in CPU instruction pipelines to guess the outcome of a conditional branch instruction to avoid pip…

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  5. GauravDhak GauravDhak Public

  6. SPI-Master-Slave-Communication-System SPI-Master-Slave-Communication-System Public

    Designed and implemented an SPI master module in Verilog for interfacing with multiple slave devices.

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