Add a new test for the not cell.

backends/lakeroad/lakeroad.cc

@@ -1246,6 +1246,7 @@ struct LakeroadWorker {
 				}
 
 				// The let-bound ID string of the expression to extract from.
+				// FIXME: On certain inputs - this never terminates. Not sure if this is a problem
 				auto extract_from_expr = get_expression_for_signal(sigmap(sig.chunks()[0].wire), -1);
 				auto new_id = get_new_id_str();
 				auto extract_expr = stringf("(Op1 (Extract %d %d) %s)", (chunk.offset + chunk.width - 1) + chunk.wire->start_offset,
@@ -1291,7 +1292,7 @@ struct LakeroadWorker {
 		f << "\n; cells\n";
 		for (auto cell : module->cells()) {
 
-			if (cell->type.in(ID($logic_not))) {
+			if (cell->type.in(ID($logic_not), ID($not))) {
 				// Unary ops.
 				assert(cell->connections().size() == 2);
 				auto y = sigmap(cell->getPort(ID::Y));
@@ -1301,6 +1302,8 @@ struct LakeroadWorker {
 				std::string op_str;
 				if (cell->type == ID($logic_not))
 					op_str = "(LogicNot)";
+				else if (cell->type == ID($not))
+					op_str = "(Not)";
 				else
 					log_error("This should be unreachable. You are missing an else if branch.\n");
 

backends/lakeroad/tests/simple-mux.ys

@@ -0,0 +1,22 @@
+read_verilog -sv <<EOF
+module test(input [2:0] a, output [2:0] out);
+  // assign out = ~ a;
+  always_comb begin
+	  case (a)
+		  2'b01: out = 2'b10;
+		  2'b00: out = 2'b10;
+		  2'b10: out = 2'b00;
+		  2'b11: out = 2'b01;
+		  default: out = 2'b01;
+	  endcase
+  end
+endmodule
+EOF
+# Optimize out the mux to simple gates.
+prep -top test; pmuxtree;
+proc; opt; memory; opt;
+techmap; opt;
+abc; opt;
+write_lakeroad
+# Writing the verilog first with "-noattr" doesn't cause infinite loop
+# write_verilog -noattr simple-mux.v

backends/lakeroad/tests/simple-mux1.ys

@@ -0,0 +1,15 @@
+read_verilog -sv <<EOF
+/* This module is generated by using "simple-mux.ys" + "write_verilog -noattr simple-mux.v". Delete this once you find the problem(most likely due to attributes). */
+module test(a, out);
+  wire _0_;
+  input [2:0] a;
+  wire [2:0] a;
+  output [2:0] out;
+  wire [2:0] out;
+  assign _0_ = a[0] & a[1];
+  assign out[1] = ~(a[1] | a[2]);
+  assign out[0] = a[2] | _0_;
+  assign out[2] = 1'h0;
+endmodule
+EOF
+write_lakeroad

backends/lakeroad/tests/simple-not.ys

@@ -0,0 +1,6 @@
+read_verilog -sv <<EOF
+module test(input a, output out);
+  assign out = ~ a;
+endmodule
+EOF
+write_lakeroad