Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

ci: add lychee to check external links #330

Closed
wants to merge 5 commits into from
Closed
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
21 changes: 0 additions & 21 deletions .github/workflows/local-link-checker.yaml

This file was deleted.

28 changes: 28 additions & 0 deletions .github/workflows/lychee.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
name: lychee

on:
push:
branches:
- master
schedule:
- cron: '0 0 1 * *'

jobs:
links:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3

- name: Link Checker
uses: lycheeverse/lychee-action@master
env:
GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
with:
args: '--verbose --max-retries 4 --no-progress "**/*.md"'

- name: Create Issue From File
uses: peter-evans/create-issue-from-file@v2
with:
title: Link Checker Report
content-filepath: ./lychee/out.md
labels: automated issue
4 changes: 4 additions & 0 deletions .lycheeignore
Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
https://talk.nervos.org/
https://discord.gg/8cWtA9uJR5
/@[^/]+
wancencen@cryptape.com
57 changes: 0 additions & 57 deletions CHANGELOG.md

This file was deleted.

2 changes: 1 addition & 1 deletion rfcs/0003-ckb-vm/0003-ckb-vm.md
Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ CKB only defines the low level virtual machine. In theory, any languages with RI
* CKB can leverage standard riscv-gcc, riscv-llvm or even upstream gcc/llvm for C/C++ contract development. Executables emitted by those compilers can be directly used as CKB contracts.
* C-based Bitcoin or Ethereum VM can also be compiled into RISC-V binaries as common cells, contracts can then load those common cells to run Bitcoin or Ethereum compatible contracts.
* Higher-level language VMs, such as [duktape](http://duktape.org/) or [mruby](https://github.com/mruby/mruby) can also be compiled and loaded to run contracts running by JavaScript or Ruby
* [Rust](https://github.com/riscv-rust/rust) can also be used to write contracts with recent development in this space
* [Rust](https://github.com/riscv-rust/riscv-rust-quickstart) can also be used to write contracts with recent development in this space

## Runtime Cost

Expand Down
2 changes: 1 addition & 1 deletion rfcs/0003-ckb-vm/0003-ckb-vm.zh.md
Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,7 @@ CKB 核心只定义了底层的虚拟机模型,理论上任何提供了 RISC-V
* CKB 可以直接使用标准的 riscv-gcc 以及 riscv-llvm 以 C/C++ 语言来进行开发。编译后的可执行文件可以直接作为 CKB 的合约来使用
* 与此相应的,可以将 C 实现的 Bitcoin 以及 Ethereum VM 编译成 RISC-V 二进制代码,保存在公共 Cell 中,然后在合约中引用公共 Cell 来运行 Bitcoin 或者 Ethereum 的合约
* 其他的高级语言 VM 如 [duktape](http://duktape.org/) 及 [mruby](https://github.com/mruby/mruby) 在编译后,也可以用来相应的运行 JavaScript 或者 Ruby 编写的合约
* 相应的也可以使用 [Rust](https://github.com/riscv-rust/rust) 作为实现语言来编写合约
* 相应的也可以使用 [Rust](https://github.com/riscv-rust/riscv-rust-quickstart) 作为实现语言来编写合约

## Runtime Cost

Expand Down
2 changes: 1 addition & 1 deletion rfcs/0005-priviledged-mode/0005-priviledged-mode.md
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ Notice privileged architecture here is an opt-in feature that is closed by defau

## Privileged mode support via CSR instructions

To ensure maximum compatibility, we will use the exact instructions and workflows defined in the [RISC-V spec](https://riscv.org/specifications/privileged-isa/) to implement privilege mode support here:
To ensure maximum compatibility, we will use the exact instructions and workflows defined in the [RISC-V spec](https://riscv.org/technical/specifications/privileged-isa/) to implement privilege mode support here:

* First, CSR instructions as defined in RISC-V will be implemented in CKB VM to implement read/write on control and status registers(CSR).
* For simplicity reasons, we might not implement every control and status register as defined in RISC-V spec. For now, we are planning to implement `Supervisor Trap Vector Base Address Register(stvec)` and any other register that might be used in the trap phase. As documented in the spec, reading/writing other registers will result in illegal instruction exception, it's up to contract writer how they want to handle this.
Expand Down
2 changes: 1 addition & 1 deletion rfcs/0005-priviledged-mode/0005-priviledged-mode.zh.md
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ Created: 2018-11-26

## 基于 CSR 指令的特权模式支持

为尽最大可能确保兼容性,我们会用 [RISC-V 标准](https://riscv.org/specifications/privileged-isa/) 中定义的指令以及流程来实现特权指令支持:
为尽最大可能确保兼容性,我们会用 [RISC-V 标准](https://riscv.org/technical/specifications/privileged-isa/) 中定义的指令以及流程来实现特权指令支持:

* 首先,我们会实现 RISC-V 标准中定义的 CSR 指令,用于读写控制与状态寄存器 (CSR)。
* 出于简化实现的考虑,我们不会实现 RISC-V 中定义的每一个控制与状态寄存器。目前为止,我们只计划实现 `Supervisor Trap Vector Base Address Register(stvec)` 以及其他在 trap 阶段会被用到的寄存器。在 CKB VM 中读写其他寄存器会参照 spec 中的定义,抛出违法指令的异常,合约开发者可以自行决定如何处理异常。
Expand Down