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csr: A proposal for DSL design #7
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Commits on Sep 24, 2019
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Commits on Sep 25, 2019
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Commits on Sep 26, 2019
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Commits on Sep 27, 2019
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Commits on Sep 30, 2019
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Commits on Oct 2, 2019
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Commits on Oct 3, 2019
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Commits on Oct 4, 2019
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Commits on Oct 14, 2019
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csr: WIP - add CSRBank to control csr r/w signal latching, add CSRBan…
…kArray, add wishbone from HeavyX
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Commits on Oct 22, 2019
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Commits on Oct 24, 2019
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Commits on Oct 30, 2019
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Commits on Nov 5, 2019
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Commits on Nov 8, 2019
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csr.dsl: better context managers, add reset strobe for Register
* Field is now a context manager: enums must be added using `with field` block, but can be read from outside using `field.Enums` * Bank & Register no longer needs `with <object> as <var>` block, only `with <object>` in order to build them with regs and fields
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Commits on Dec 6, 2019
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csr: Bank now can either be a Decoder or a Mux; add tests
* Bank now only aligns register addresses without resizing the registers
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Commits on Jan 8, 2020
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Commits on Jan 13, 2020
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csr: fix bitmasked r/w logic, add dsl.Register for WBCSRBridge tests
* Register bits in locations that are not occupied by any Fields are now regular Signals, with no access restrictions (i.e. treated as don't care). * Any attempt to read or write these bits via a bus will return or change their values without any restrictions.
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Commits on Jan 15, 2020
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csr.dsl: replace by-Field signals with Register-wide signal; fix alias
* Instead of storing a Signal in each Field, each Register now store a single Signal comprising of both Field bits and "don't care" bits * Each Field object no longer carries a value, but only the information needed to describe a Register (e.g. bit locations, access mode, enumerated values)
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Commits on Jan 17, 2020
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csr.dsl: add logic for internal writes
* Add an internal write strobe (`set_stb`/`set_enable`/`set_en`/`int_w_stb`) to Register and Field; asserted when the logic reassigns the values and overrides any writes from the bus. * Add an internal write data signal (`set_val`/`set_value`/`int_w_data`) to Register; contains the data that the logic uses to reassign the Register or Field values when `set_stb` is asserted. * Each Field now allows value assignments from the following sources: (The smaller the number, the higher the priority) (1) Bank reset strobe (`Bank.rst_stb`): when asserted, reset all its Registers in the Bank to their reset values at the next clock (2) Register reset strobe (`Register.rst_stb`): when asserted, reset all its Fields to their reset values and the remaining bits to 0 at the next clock (3) Register internal write strobe (`Register.set_stb`): when asserted, set all its Fields to their own current `Field.set_val` value at the next clock (4) Field internal write strobe (`Field.set_stb`): when asserted, set the Field to its own current `Field.set_val` value at the next clock (5) Register bus write strobe (`Register.w_stb`): when asserted, set all its Fields to the current `Element.w_data` value at the next clock * When either `Bank.rst_stb` or `Register.rst_stb` is asserted while `bus.rst_stb` is high, each Register now returns the reset value to `Element.r_data` for reading immediately
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Commits on Jan 23, 2020
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Commits on Jan 31, 2020
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Commits on Feb 1, 2020
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Commits on Mar 1, 2020
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Commits on Apr 29, 2020
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