sync verilog with previous commit

litex-hub · Apr 25, 2024 · 1979a64 · 1979a64
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diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 
@@ -38,6 +38,7 @@ module VexRiscv (
   input  wire          dBusWishbone_ERR,
   output wire [2:0]    dBusWishbone_CTI,
   output wire [1:0]    dBusWishbone_BTE,
+  output wire          halted,
   input  wire          clk,
   input  wire          reset,
   input  wire          debugReset
@@ -4763,6 +4764,7 @@ module VexRiscv (
   assign dBus_rsp_valid = _zz_dBus_rsp_valid;
   assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
   assign dBus_rsp_payload_error = 1'b0;
+  assign halted = DebugPlugin_haltIt;
   always @(posedge clk) begin
     if(reset) begin
       IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 
@@ -46,6 +46,7 @@ module VexRiscv (
   input  wire          dBusWishbone_ERR,
   output wire [2:0]    dBusWishbone_CTI,
   output wire [1:0]    dBusWishbone_BTE,
+  output wire          halted,
   input  wire          clk,
   input  wire          reset,
   input  wire          debugReset
@@ -5314,6 +5315,7 @@ module VexRiscv (
   assign dBus_rsp_valid = _zz_dBus_rsp_valid;
   assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
   assign dBus_rsp_payload_error = 1'b0;
+  assign halted = DebugPlugin_haltIt;
   always @(posedge clk) begin
     if(reset) begin
       IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 
@@ -38,6 +38,7 @@ module VexRiscv (
   input  wire          dBusWishbone_ERR,
   output wire [2:0]    dBusWishbone_CTI,
   output wire [1:0]    dBusWishbone_BTE,
+  output wire          halted,
   input  wire          clk,
   input  wire          reset,
   input  wire          debugReset
@@ -5045,6 +5046,7 @@ module VexRiscv (
   assign dBus_rsp_valid = _zz_dBus_rsp_valid;
   assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
   assign dBus_rsp_payload_error = 1'b0;
+  assign halted = DebugPlugin_haltIt;
   always @(posedge clk) begin
     if(reset) begin
       IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 
@@ -38,6 +38,7 @@ module VexRiscv (
   input  wire          dBusWishbone_ERR,
   output wire [2:0]    dBusWishbone_CTI,
   output wire [1:0]    dBusWishbone_BTE,
+  output wire          halted,
   input  wire          clk,
   input  wire          reset,
   input  wire          debugReset
@@ -5337,6 +5338,7 @@ module VexRiscv (
   assign dBus_rsp_valid = _zz_dBus_rsp_valid;
   assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
   assign dBus_rsp_payload_error = 1'b0;
+  assign halted = DebugPlugin_haltIt;
   always @(posedge clk) begin
     if(reset) begin
       IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 
@@ -38,6 +38,7 @@ module VexRiscv (
   input  wire          dBusWishbone_ERR,
   output wire [2:0]    dBusWishbone_CTI,
   output wire [1:0]    dBusWishbone_BTE,
+  output wire          halted,
   input  wire          clk,
   input  wire          reset,
   input  wire          debugReset
@@ -6361,6 +6362,7 @@ module VexRiscv (
   assign dBus_rsp_valid = _zz_dBus_rsp_valid;
   assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
   assign dBus_rsp_payload_error = 1'b0;
+  assign halted = DebugPlugin_haltIt;
   always @(posedge clk) begin
     if(reset) begin
       IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 
@@ -38,6 +38,7 @@ module VexRiscv (
   input  wire          dBusWishbone_ERR,
   output wire [2:0]    dBusWishbone_CTI,
   output wire [1:0]    dBusWishbone_BTE,
+  output wire          halted,
   input  wire          clk,
   input  wire          reset,
   input  wire          debugReset
@@ -4258,6 +4259,7 @@ module VexRiscv (
   assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
   assign dBus_rsp_data = dBusWishbone_DAT_MISO;
   assign dBus_rsp_error = 1'b0;
+  assign halted = DebugPlugin_haltIt;
   always @(posedge clk) begin
     if(reset) begin
       IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 
@@ -38,6 +38,7 @@ module VexRiscv (
   input  wire          dBusWishbone_ERR,
   output wire [2:0]    dBusWishbone_CTI,
   output wire [1:0]    dBusWishbone_BTE,
+  output wire          halted,
   input  wire          clk,
   input  wire          reset,
   input  wire          debugReset
@@ -4266,6 +4267,7 @@ module VexRiscv (
   assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
   assign dBus_rsp_data = dBusWishbone_DAT_MISO;
   assign dBus_rsp_error = 1'b0;
+  assign halted = DebugPlugin_haltIt;
   always @(posedge clk) begin
     if(reset) begin
       IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 
@@ -38,6 +38,7 @@ module VexRiscv (
   input  wire          dBusWishbone_ERR,
   output wire [2:0]    dBusWishbone_CTI,
   output wire [1:0]    dBusWishbone_BTE,
+  output wire          halted,
   input  wire          clk,
   input  wire          reset,
   input  wire          debugReset
@@ -3494,6 +3495,7 @@ module VexRiscv (
   assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
   assign dBus_rsp_data = dBusWishbone_DAT_MISO;
   assign dBus_rsp_error = 1'b0;
+  assign halted = DebugPlugin_haltIt;
   assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_flush = 1'b0;
   always @(posedge clk) begin
     if(reset) begin

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 
@@ -38,6 +38,7 @@ module VexRiscv (
   input  wire          dBusWishbone_ERR,
   output wire [2:0]    dBusWishbone_CTI,
   output wire [1:0]    dBusWishbone_BTE,
+  output wire          halted,
   input  wire          clk,
   input  wire          reset,
   input  wire          debugReset
@@ -3502,6 +3503,7 @@ module VexRiscv (
   assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
   assign dBus_rsp_data = dBusWishbone_DAT_MISO;
   assign dBus_rsp_error = 1'b0;
+  assign halted = DebugPlugin_haltIt;
   assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_flush = 1'b0;
   always @(posedge clk) begin
     if(reset) begin

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 

diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v
@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.9.4    git head : 270018552577f3bb8e5339ee2583c9c22d324215
 // Component : VexRiscv
-// Git hash  : 63430af99f84cc1d11d58b556debe1cc3f238c67
+// Git hash  : 8542a5786b26857f3ef830ae9e72eec031df42d3
 
 `timescale 1ns/1ps
 
@@ -38,6 +38,7 @@ module VexRiscv (
   input  wire          dBusWishbone_ERR,
   output wire [2:0]    dBusWishbone_CTI,
   output wire [1:0]    dBusWishbone_BTE,
+  output wire          halted,
   input  wire          clk,
   input  wire          reset,
   input  wire          debugReset
@@ -8541,6 +8542,7 @@ module VexRiscv (
   assign dBus_rsp_valid = _zz_dBus_rsp_valid;
   assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
   assign dBus_rsp_payload_error = 1'b0;
+  assign halted = DebugPlugin_haltIt;
   always @(posedge clk) begin
     if(reset) begin
       IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;