Merge pull request #20 from lschuermann/dev/pmp-plugin-switch

Update VexRiscv to `b6118e6cc2a3`, sbt to 1.9.7, SpinalHDL to 1.9.4; make PMP plugin selection configurable
litex-hub · Nov 20, 2023 · 03d8c47 · 03d8c47
2 parents a36d99e + 1aead15
commit 03d8c47
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diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv.v b/pythondata_cpu_vexriscv/verilog/VexRiscv.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/build.sbt b/pythondata_cpu_vexriscv/verilog/build.sbt
@@ -1,11 +1,11 @@
-val spinalVersion = "1.6.0"
+val spinalVersion = "1.9.4"
 
 lazy val root = (project in file(".")).
   settings(
     inThisBuild(List(
       organization := "com.github.spinalhdl",
       scalaVersion := "2.11.12",
-      version      := "0.1.0-SNAPSHOT"
+      version      := "2.0.0"
     )),
     name := "VexRiscvOnWishbone",
     libraryDependencies ++= Seq(

diff --git a/pythondata_cpu_vexriscv/verilog/ext/VexRiscv b/pythondata_cpu_vexriscv/verilog/ext/VexRiscv
diff --git a/pythondata_cpu_vexriscv/verilog/project/build.properties b/pythondata_cpu_vexriscv/verilog/project/build.properties
@@ -1 +1 @@
-sbt.version=1.2.7
+sbt.version=1.9.7
diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala
@@ -27,6 +27,7 @@ case class ArgConfig(
   dCacheSize : Int = 4096,
   pmpRegions : Int = 0,
   pmpGranularity : Int = 256,
+  pmpAddressMatchingModes : String = "na4,napot,tor",
   mulDiv : Boolean = true,
   cfu : Boolean = false,
   atomics: Boolean = false,
@@ -68,6 +69,7 @@ object GenCoreDefault{
       opt[Int]("dCacheSize")     action { (v, c) => c.copy(dCacheSize = v) } text("Set data cache size, 0 mean no cache")
       opt[Int]("pmpRegions")    action { (v, c) => c.copy(pmpRegions = v)   } text("Number of PMP regions, 0 disables PMP")
       opt[Int]("pmpGranularity")    action { (v, c) => c.copy(pmpGranularity = v)   } text("Granularity of PMP regions (in bytes)")
+      opt[String]("pmpAddressMatchingModes")    action { (v, c) => c.copy(pmpAddressMatchingModes = v)   } text("Which PMP address matching modes to support (comma-separated, out of [NA4, NAPOT, TOR])")
       opt[Boolean]("mulDiv")    action { (v, c) => c.copy(mulDiv = v)   } text("set RV32IM")
       opt[Boolean]("cfu")       action { (v, c) => c.copy(cfu = v)   } text("If true, add custom function unit interface")
       opt[Boolean]("atomics")    action { (v, c) => c.copy(atomics = v)   } text("set RV32I[A]")
@@ -159,9 +161,30 @@ object GenCoreDefault{
         },
         if (linux) new MmuPlugin(
           ioRange = (x => x(31 downto 28) === 0xB || x(31 downto 28) === 0xE || x(31 downto 28) === 0xF)
-        ) else if (argConfig.pmpRegions > 0) new PmpPlugin(
-          regions = argConfig.pmpRegions, granularity = argConfig.pmpGranularity, ioRange = _.msb
-        ) else new StaticMemoryTranslatorPlugin(
+        ) else if (argConfig.pmpRegions > 0) {
+          val splitModes = argConfig.pmpAddressMatchingModes.toLowerCase().split(",");
+
+          // Ensure the user didn't request any unsupported modes
+          val unknownModes = splitModes.filterNot(s => List("na4", "napot", "tor").contains(s));
+          if (unknownModes.length > 0) {
+            throw new Exception("Unknown PMP addressing mode: " + unknownModes(0));
+          }
+
+          if (splitModes.sameElements(List("napot"))) {
+            println("Using optimized PmpPluginNapot, supporting only the NAPOT addressing mode.");
+            new PmpPluginNapot(
+              regions = argConfig.pmpRegions,
+              granularity = argConfig.pmpGranularity,
+              ioRange = _.msb
+            )
+          } else {
+            println("Using PmpPlugin supporting the NA4, NAPOT, and TOR addressing modes.");
+            println("This will ignore the pmpGranularity argument and have 4-byte granularity.");
+            new PmpPlugin (
+              regions = 16, ioRange = _.msb
+            )
+          }
+        } else new StaticMemoryTranslatorPlugin(
           ioRange      = _.msb
         ),