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Support needUpdate and defaultUpdate for DifftestBaseBundle (OpenXian…
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…gShan#262)

The valid bits are actually defined in the base bundle.
Thus, we move them from DifftestBundle to DifftestBaseBundle.
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poemonsense authored Jan 20, 2024
1 parent 08260b4 commit 09ad1b2
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Showing 4 changed files with 17 additions and 5 deletions.
15 changes: 15 additions & 0 deletions src/main/scala/Bundles.scala
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,14 @@ sealed trait DifftestBaseBundle extends Bundle {
}
}

def needUpdate: Option[Bool] = if (hasValid) Some(getValid) else None
def defaultUpdate(): DifftestBaseBundle = {
if (hasValid) {
getValid := false.B
}
this
}

def hasAddress: Boolean = this.isInstanceOf[HasAddress]
def getNumElements: Int = {
this match {
Expand Down Expand Up @@ -89,6 +97,13 @@ class TrapEvent extends DifftestBaseBundle {

val code = UInt(3.W)
val pc = UInt(64.W)

override def needUpdate: Option[Bool] = Some(hasTrap || hasWFI)
override def defaultUpdate(): TrapEvent = {
hasTrap := false.B
hasWFI := false.B
this
}
}

class CSRState extends DifftestBaseBundle {
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3 changes: 0 additions & 3 deletions src/main/scala/Difftest.scala
Original file line number Diff line number Diff line change
Expand Up @@ -56,8 +56,6 @@ sealed trait DifftestBundle extends Bundle with DifftestWithCoreid { this: Difft
}
}

def needUpdate: Option[Bool] = if (hasValid) Some(getValid) else None

protected val needFlatten: Boolean = false
def isFlatten: Boolean = hasAddress && this.needFlatten

Expand Down Expand Up @@ -142,7 +140,6 @@ class DiffInstrCommit(nPhyRegs: Int = 32) extends InstrCommit(nPhyRegs)

class DiffTrapEvent extends TrapEvent with DifftestBundle {
override val desiredCppName: String = "trap"
override def needUpdate: Option[Bool] = Some(hasTrap || hasWFI)
override def supportsSquashBase: Bool = !hasTrap && !hasWFI
}

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2 changes: 1 addition & 1 deletion src/main/scala/Gateway.scala
Original file line number Diff line number Diff line change
Expand Up @@ -183,7 +183,7 @@ class GatewayEndpoint(signals: Seq[DifftestBundle], config: GatewayConfig) exten

val global_enable = WireInit(true.B)
if(config.hasGlobalEnable) {
global_enable := VecInit(out.filter(_.needUpdate.isDefined).map(_.needUpdate.get).toSeq).asUInt.orR
global_enable := VecInit(out.flatMap(_.bits.needUpdate).toSeq).asUInt.orR
}

val batch_data = Option.when(config.isBatch)(Mem(config.batchSize, out_pack.cloneType))
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2 changes: 1 addition & 1 deletion src/main/scala/Squash.scala
Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ class SquashEndpoint(bundles: Seq[DifftestBundle], config: GatewayConfig) extend
// ignore useless unsquashed data when hasGlobalEnable
val needStore = WireInit(true.B)
if (config.hasGlobalEnable) {
needStore := VecInit(in.filter(_.needUpdate.isDefined).map(_.needUpdate.get).toSeq).asUInt.orR
needStore := VecInit(in.flatMap(_.bits.needUpdate).toSeq).asUInt.orR
}
when ((should_tick || do_squash.asUInt.orR) && needStore && !control.replay.get) {
replay_data(replay_ptr) := in
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