GitHub - gagan405/BRisk: Basic RISC Processor (Classic 5 stage pipelined)

gagan405 / BRisk Public

Notifications You must be signed in to change notification settings
Fork 2
Star 2

Basic RISC Processor (Classic 5 stage pipelined)

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
README		README
alu.vhd		alu.vhd
cache.vhd		cache.vhd
cpu.vhd		cpu.vhd
fw_mux.vhd		fw_mux.vhd
instruction_decode.vhd		instruction_decode.vhd
instruction_execute.vhd		instruction_execute.vhd
instruction_fetch.vhd		instruction_fetch.vhd
load_store.vhd		load_store.vhd
mem_arbiter.vhd		mem_arbiter.vhd
opcode_disassembler.vhd		opcode_disassembler.vhd
test.asm		test.asm
types.vhd		types.vhd

Repository files navigation

This project contains the VHDL implementation of a classic five stage pipelined processor, the one you see in the famous book of Computer Architecture by John Hennessey and David Patterson.

It can be referred by beginners to get a feeling of the pipelined implementation of a simple RISC core. But standalone, this cannot be synthesized or simulated, as various modules such as SRAM and clock generator etc. are not avaialable here.

This was developed as part of a lab course at the University of Stuttgart, Germany.