Introduction to Efabless Caravel

The Efabless Caravel chip is a ready-to-use test harness for creating designs with the Google/Skywater 130nm Open PDK. The Caravel harness comprises of base functions supporting IO, power and configuration as well as drop-in modules for a management SoC core. The current SoC architecture is given below.

Caravel Lab Purpose

• Integrate a custom RTL design to Caravel SoC
• Go through overall Caravel user flow and ready to MPW submission

Caravel Lab Prerequisites

• Ubuntu 20.04+
• Installed Docker packages
• Icarus Verilog Windows version 12.0 bundled with GTKWave
• Caravel user project sources with tag mpw-8c
• Download and unzip caravel lab data

1. Custom RTL Design

A GCD design and testbench sources located in custom_design/gcd/source. The design example was verified under Icarus Verilog and GTKWave.

$ iverilog seq_gcd.v testbench.v  && vvp a.out
VCD info: dumpfile dump.vcd opened for output.
             Result is correct:  GCD(  10312050,  29460792) -->: Expected =        138; Actual Result =        138
             Result is correct:  GCD(1993627629,1177417612) -->: Expected =          7; Actual Result =          7
             Result is correct:  GCD(2097015289,3812041926) -->: Expected =          1; Actual Result =          1
             Result is correct:  GCD(1924134885,3151131255) -->: Expected =        135; Actual Result =        135
             Result is correct:  GCD( 992211318, 512609597) -->: Expected =          1; Actual Result =          1
testbench.v:100: $stop called at 609 (1s)
** VVP Stop(0) **
** Flushing output streams.
** Current simulation time is 609 ticks.
> finish
** Continue **

We use GTKWave to read saved signals (golden.gtkw) from dump.vcd. The following timing diagram shows GCD(10312050, 29460792)=138

$ gtkwave golden.gtkw

Further, GCD's Openlane configuration file config.json was tested under individual Openlane flow with PDK sky130_fd_sc_hd and clock period 80 ns.

2. Caravel User Flow

The below instructions show Caravel user flow setup and execution step-by-step with custom GCD RTL design example.

• Execute 'export PATH=$PATH:~/.local/bin' before first time 'make setup'. There is a 'volare: command not found' issue referred from offical troubleshooting.
• The three variables OPENLANE_ROOT, PDK_ROOT and PDK always are needed to export before Caravel user flow execution. In Caravel lab, you need to change directory to ~/caravel_user_project firstly and then export the three variables.
• Download custom_design to your experimental environment.
• The GCD design was wrapped with logic analyzer input/output in user_proj_example.v, which can be triggered by la_test1.c and monitored by la_test1_tb.v.
• After RTL simulation, you can find a VCD waveform file RTL-la_test1.vcd updated in ~/caravel_user_project/verilog/dv/la_test1/ and debug it with GTKWave tool.
• Caravel SoC memory map definition and testbench examples.
• We change default "RUN_CVC" : 1 to 0 in user project example's config.json to skip not working Openlane CVC step in Caravel user flow.
• The gate level static timing verifier is based on OpenROAD OpenSTA.
• In MPW precheck, you have to update two files to pass check (1) update README.md (>25% difference) to replace original one (2) change 13'hXXXX to 13'h0000 in user_defines.v.

All Caravel user flow step outputs were written to log files.

Setup caravel_user_project    
$ git clone -b mpw-8c https://github.com/efabless/caravel_user_project ~/caravel_user_project
$ cd ~/caravel_user_project
$ mkdir dependencies
$ export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src
$ export PDK_ROOT=$(pwd)/dependencies/pdks
$ export PDK=sky130A    
$ make setup

Run RTL simulation
$ cp ~/caravel-lab/custom_design/gcd/user_proj_example/user_proj_example.v ~/caravel_user_project/verilog/rtl/user_proj_example.v
$ cp ~/caravel-lab/custom_design/gcd/verify-la_test1-rtl/la_test1.c ~/caravel_user_project/verilog/dv/la_test1/la_test1.c
$ cp ~/caravel-lab/custom_design/gcd/verify-la_test1-rtl/la_test1_tb.v ~/caravel_user_project/verilog/dv/la_test1/la_test1_tb.v
$ make simenv
$ SIM=RTL
$ make verify-la_test1-rtl

Run Openlane to generate RTL netlist
$ cp ~/caravel-lab/custom_design/gcd/user_proj_example/config.json ~/caravel_user_project/openlane/user_proj_example/config.json
$ cd openlane
$ make user_proj_example
$ make user_project_wrapper

Run gate level simulation (it will take 2~3 hours@i9/64GB)
$ cd ..
$ SIM=GL    
$ make verify-la_test1-gl

Run gate level static timing verifier
$ make setup-timing-scripts
$ make extract-parasitics
$ make create-spef-mapping
$ make caravel-sta

Run MPW precheck
$ cp ~/caravel-lab/custom_design/gcd/mpw_precheck/README.md ~/caravel_user_project/README.md
$ cp ~/caravel-lab/custom_design/gcd/mpw_precheck/user_defines.v  ~/caravel_user_project/verilog/rtl/user_defines.v
$ make precheck
$ make run-precheck

Caravel user flow step logs

• setup-caravel_user_project.log
• run-rtl-simulation.log
• run-openlane-to-generate-rtl-netlist.log
• run-gate-level-simulation (same as run-rtl-simulation.log but take a long time)
• run-gate-level-static-timing-verifier.log
• run-mpw-precheck.log

Checklist for Open-MPW Submission & MPW Public Project

Finally, you need to comply with offical checklist to upload your MPW public project.

Offical Documents

• Quickstart of How to Use Caravel User Project
• Caravel User Project
• Efabless Caravel “harness” SoC
• Efabless Caravel Specification