Fix verilog file parsing error

[joeywang4]

When the parser encounters a gate name, it will not skip this name but throws an error of expected opening parenthesis.
For example, the following verilog file will cause this error:

module top(x1, x2, z);
    input x1, x2;
    output z;
    and aaa(z, x1, x2); // Error due to the gate name "aaa"
endmodule

I fixed this bug by simply calling the Ver_ParseGetName function to skip the gate name.

[functionpointer]

Encountered this bug too. Great fix!