This is pong, written in Verilog, for the Altera DE1_SoC FPGA.
Input: Buttons for paddle control, switches for settings Output: VGA monitor in 640x480 with 24bit color. 7-Seg Score
This was built for my final project for EE 271 at the University of Washington
Video link here: https://www.youtube.com/watch?v=aYI0aAUlaNc