Release version 0.46

CHANGELOG

@@ -2,8 +2,28 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.45 .. Yosys 0.46-dev
+Yosys 0.45 .. Yosys 0.46
 --------------------------
+ * Various
+ - Added new "functional backend" infrastructure with three example
+ backends (C++, SMTLIB and Rosette).
+ - Added new coarse-grain buffer cell type "$buf" to RTLIL.
+ - Added "-y" command line option to execute a Python script with 
+ libyosys available as a built-in module.
+ - Added support for casting to type in Verilog frontend.
+
+ * New commands and options
+ - Added "clockgate" pass for automatic clock gating cell insertion.
+ - Added "bufnorm" experimental pass to convert design into
+ buffered-normalized form.
+ - Added experimental "aiger2" and "xaiger2" backends, and an 
+ experimental "abc_new" command
+ - Added "-force-detailed-loop-check" option to "check" pass.
+ - Added "-unit_delay" option to "read_liberty" pass.
+
+ * Verific support
+ - Added left and right bound properties to wires when using
+ specific VHDL types.
 
 Yosys 0.44 .. Yosys 0.45
 --------------------------

Makefile

@@ -154,7 +154,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.45+240
+YOSYS_VER := 0.46
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -170,7 +170,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
- sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile
+# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 

docs/source/conf.py

@@ -5,7 +5,7 @@
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2024 YosysHQ GmbH'
-yosys_ver = "0.45"
+yosys_ver = "0.46"
 
 # select HTML theme
 html_theme = 'furo'