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fmax: litex soc now forced to keep tilelink timing buffers
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Dolu1990 committed Jul 1, 2024
1 parent aa38c72 commit 636acee
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Showing 2 changed files with 5 additions and 5 deletions.
2 changes: 1 addition & 1 deletion ext/SpinalHDL
8 changes: 4 additions & 4 deletions src/main/scala/vexiiriscv/soc/litex/Soc.scala
Original file line number Diff line number Diff line change
Expand Up @@ -60,8 +60,8 @@ class Soc(c : SocConfig, systemCd : ClockDomain) extends Component{
for (vexii <- vexiis) {
if (vexiiParam.fetchL1Enable) vexii.iBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S)
if (vexiiParam.lsuL1Enable) {
vexii.lsuL1Bus.setDownConnection(a = withCoherency.mux(StreamPipe.HALF, StreamPipe.FULL), b = StreamPipe.HALF, c = StreamPipe.FULL, d = StreamPipe.M2S, e = StreamPipe.HALF)
vexii.dBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S)
vexii.lsuL1Bus.setDownConnection(a = withCoherency.mux(StreamPipe.HALF, StreamPipe.FULL), b = StreamPipe.HALF_KEEP, c = StreamPipe.FULL, d = StreamPipe.M2S_KEEP, e = StreamPipe.HALF)
vexii.dBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S_KEEP)
}
}

Expand Down Expand Up @@ -355,11 +355,11 @@ object PythonArgsGen extends App{

/*
--lsu-software-prefetch --lsu-hardware-prefetch
# debian 4c
python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --cpu-variant=debian --with-jtag-tap --bus-standard axi-lite \
--vexii-args="--performance-counters 9 --regfile-async --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --lsu-l1-store-buffer-slots=2" \
--vexii-args="--lsu-software-prefetch --lsu-hardware-prefetch --performance-counters 9 --regfile-async --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --lsu-l1-store-buffer-slots=2" \
--cpu-count=4 --with-jtag-tap --with-video-framebuffer --l2-self-flush=40c00000,40dd4c00,1666666 --with-sdcard --with-ethernet --with-coherent-dma --l2-byte=262144 --sys-clk-freq 100000000 \
--update-repo=no --soc-json build/csr.json --build --load
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