Fix fetch next line prefetcher

SpinalHDL · Oct 22, 2024 · 4e3be31 · 4e3be31
1 parent 2d24a50
commit 4e3be31
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Showing 4 changed files with 12 additions and 6 deletions.
diff --git a/ext/NaxSoftware b/ext/NaxSoftware
diff --git a/src/main/scala/vexiiriscv/fetch/Prefetch.scala b/src/main/scala/vexiiriscv/fetch/Prefetch.scala
@@ -39,7 +39,7 @@ class PrefetcherNextLinePlugin(lineSize : Int) extends PrefetcherPlugin{
 
     val probeAddressNext = KeepAttribute(io.probe.pc + lineSize)
     val address = Reg(Global.PC)
-    val addressHit = address === io.probe.pc
+    val addressHit = address.dropLow(log2Up(lineSize)) === io.probe.pc.dropLow(log2Up(lineSize))
 
     val unbuffered = Stream(PrefetchCmd())
     unbuffered.valid := False

diff --git a/src/main/tcl/openocd/no_prefetch.tcl b/src/main/tcl/openocd/no_prefetch.tcl
@@ -1,12 +1,16 @@
+for {set i 0} {$i < $cpu_count} {incr i} {
+    targets $_TARGETNAME.$i
+    halt
+}
 
 for {set i 0} {$i < $cpu_count} {incr i} {
     targets $_TARGETNAME.$i
-    reg 2112 0x3
+    reg 2112 0x2
 }
 
 for {set i 0} {$i < $cpu_count} {incr i} {
     targets $_TARGETNAME.$i
     resume
 }
 
-exit
+
diff --git a/src/main/tcl/openocd/with_prefetch.tcl b/src/main/tcl/openocd/with_prefetch.tcl
@@ -1,3 +1,7 @@
+for {set i 0} {$i < $cpu_count} {incr i} {
+    targets $_TARGETNAME.$i
+    halt
+}
 
 for {set i 0} {$i < $cpu_count} {incr i} {
     targets $_TARGETNAME.$i
@@ -8,5 +12,3 @@ for {set i 0} {$i < $cpu_count} {incr i} {
     targets $_TARGETNAME.$i
     resume
 }
-
-exit