Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Validate: update ArchRegState only when commit or event #488

Merged
merged 1 commit into from
Oct 30, 2024
Merged

Validate: update ArchRegState only when commit or event #488

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions src/main/scala/Difftest.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -298,6 +298,7 @@ class DiffVecWriteback(numRegs: Int = 32) extends DiffIntWriteback(numRegs) {
class DiffArchIntRegState extends ArchIntRegState with DifftestBundle {
override val desiredCppName: String = "regs_int"
override val desiredOffset: Int = 0
override val updateDependency: Seq[String] = Seq("commit", "event")
}

abstract class DiffArchDelayedUpdate(numRegs: Int)
Expand All @@ -318,11 +319,13 @@ class DiffArchFpDelayedUpdate extends DiffArchDelayedUpdate(32) {
class DiffArchFpRegState extends ArchIntRegState with DifftestBundle {
override val desiredCppName: String = "regs_fp"
override val desiredOffset: Int = 2
override val updateDependency: Seq[String] = Seq("commit", "event")
}

class DiffArchVecRegState extends ArchVecRegState with DifftestBundle {
override val desiredCppName: String = "regs_vec"
override val desiredOffset: Int = 4
override val updateDependency: Seq[String] = Seq("commit", "event")
}

class DiffVecCSRState extends VecCSRState with DifftestBundle {
Expand Down