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difftest: fix instances of generated Svh Interface
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Previous in PR #483 we generate interface according to collected
instances by Gateway. However, these collected instances have
already been processed by Gateway and different from original.

To generated original interface, we use Instances from Jsonprofile
directly to avoid impact of Gateway optimization
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klin02 committed Oct 28, 2024
1 parent 938e158 commit c761281
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Showing 2 changed files with 6 additions and 3 deletions.
4 changes: 2 additions & 2 deletions src/main/scala/Difftest.scala
Original file line number Diff line number Diff line change
Expand Up @@ -527,11 +527,11 @@ object DifftestModule {
difftest
}

def generateSvhInterface(numCores: Int): Unit = {
def generateSvhInterface(instances: Seq[DifftestBundle], numCores: Int): Unit = {
// generate interface by jsonProfile, single-core interface will be copied numCore times
val difftestSvh = ListBuffer.empty[String]
val core_if_len = instances.length / numCores
val gateway_args = instances.toSeq.zipWithIndex.map { case (b, idx) =>
val gateway_args = instances.zipWithIndex.map { case (b, idx) =>
val typeString = s"logic [${b.getWidth - 1}: 0]"
val argName = s"gateway_$idx"
(typeString, argName)
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5 changes: 4 additions & 1 deletion src/test/scala/DifftestTop.scala
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ import chisel3._

import java.nio.file.{Files, Paths}
import scala.annotation.tailrec
import scala.collection.mutable.ListBuffer
import org.json4s.DefaultFormats
import org.json4s.native.JsonMethods.parse

Expand Down Expand Up @@ -64,6 +65,7 @@ class DifftestTop extends Module {

// Generate simulation interface based on Profile describing the instantiated information of design
class SimTop(profileName: String, numCores: Int) extends Module {
val instances = ListBuffer.empty[DifftestBundle]
val profileStr = new String(Files.readAllBytes(Paths.get(profileName)))
val profiles = parse(profileStr).extract[List[Map[String, Any]]](DefaultFormats, manifest[List[Map[String, Any]]])
for (coreid <- 0 until numCores) {
Expand All @@ -77,12 +79,13 @@ class SimTop(profileName: String, numCores: Int) extends Module {
val constructor = Class.forName(prof("className").toString).getConstructors()(0)
val args = constructor.getParameters().toSeq.map { param => prof(param.getName.toString) }
val inst = constructor.newInstance(args: _*).asInstanceOf[DifftestBundle]
instances += inst
DifftestModule(inst, true, prof("delay").asInstanceOf[Int]).suggestName(s"gateway_${coreid}_$idx")
}
}
val dutInfo = profiles.find(_.contains("cpu")).get
DifftestModule.generateSvhInterface(instances.toSeq, numCores)
DifftestModule.finish(dutInfo("cpu").asInstanceOf[String])
DifftestModule.generateSvhInterface(numCores)
}

abstract class DifftestApp extends App {
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