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fix(csr): add difftest of mhpmevent overflow to diff csr mhpmeventn #3788

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fix(csr): add difftest of mhpmevent overflow to diff csr mhpmeventn #3788

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e77465c
fix(CSR): remove reg in `scountovf`.
wissygh Sep 30, 2024
d08a73c
fix(mhpmevent): add MhpmeventBundle for mhpmevent csr.
wissygh Oct 9, 2024
3572df9
fix(csr): add difftest of mhpmevent overflow to diff csr mhpmeventn
sinceforYy Oct 10, 2024
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63 changes: 36 additions & 27 deletions src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ import xiangshan.backend.fu.NewCSR.CSREnumTypeImplicitCast._
import xiangshan.backend.fu.NewCSR.ChiselRecordForField._
import xiangshan.backend.fu.PerfCounterIO
import xiangshan.backend.fu.NewCSR.CSRConfig._
import xiangshan.backend.fu.NewCSR.CSRFunc.wNoEffectWhen
import xiangshan.backend.fu.NewCSR.CSRFunc._

import scala.collection.immutable.SeqMap

Expand Down Expand Up @@ -165,8 +165,12 @@ trait MachineLevel { self: NewCSR =>
.setAddr(CSRs.mcountinhibit)

val mhpmevents: Seq[CSRModule[_]] = (3 to 0x1F).map(num =>
Module(new CSRModule(s"Mhpmevent$num") with HasPerfEventBundle {
regOut := this.perfEvents(num - 3)
Module(new CSRModule(s"Mhpmevent$num", new MhpmeventBundle) with HasOfFromPerfCntBundle {
when(wen){
reg.OF := wdata.OF
}.elsewhen(ofFromPerfCnt) {
reg.OF := ofFromPerfCnt
}
})
.setAddr(CSRs.mhpmevent3 - 3 + num)
)
Expand Down Expand Up @@ -418,20 +422,6 @@ trait MachineLevel { self: NewCSR =>
machineLevelCSRMods.map(csr => (csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt)).iterator
)

// read/write/update mhpmevents -> read/write/update perfEvents
val perfEvents = List.fill(8)(RegInit("h0000000000".U(XLEN.W))) ++
List.fill(8)(RegInit("h4010040100".U(XLEN.W))) ++
List.fill(8)(RegInit("h8020080200".U(XLEN.W))) ++
List.fill(5)(RegInit("hc0300c0300".U(XLEN.W)))

mhpmevents.foreach { mod =>
mod match {
case m: HasPerfEventBundle =>
m.perfEvents := perfEvents
case _ =>
}
}

}

class MstatusBundle extends CSRBundle {
Expand Down Expand Up @@ -630,16 +620,6 @@ class Mtval2Bundle extends FieldInitBundle

class MhpmcounterBundle extends FieldInitBundle

// todo: for the future, delete bypass between mhpmevents and perfEvents
class MhpmeventBundle extends CSRBundle {
val OF = RW(63).withReset(0.U)
val MINH = RW(62).withReset(0.U)
val SINH = RW(61).withReset(0.U)
val UINH = RW(60).withReset(0.U)
val VSINH = RW(59).withReset(0.U)
val VUINH = RW(58).withReset(0.U)
}

class MEnvCfg extends EnvCfg {
if (CSRConfig.EXT_SSTC) {
this.STCE.setRW().withReset(1.U)
Expand Down Expand Up @@ -684,6 +664,35 @@ class MipToMvip extends IpValidBundle {
this.SEIP.bits.setRW()
}

class MhpmeventBundle extends CSRBundle {
val OF = RW(63).withReset(0.U)
val MINH = RW(62).withReset(0.U)
val SINH = RW(61).withReset(0.U)
val UINH = RW(60).withReset(0.U)
val VSINH = RW(59).withReset(0.U)
val VUINH = RW(58).withReset(0.U)
val OPTYPE2 = OPTYPE(54, 50, wNoFilter).withReset(OPTYPE.OR)
val OPTYPE1 = OPTYPE(49, 45, wNoFilter).withReset(OPTYPE.OR)
val OPTYPE0 = OPTYPE(44, 40, wNoFilter).withReset(OPTYPE.OR)
val EVENT3 = RW(39, 30).withReset(0.U)
val EVENT2 = RW(29, 20).withReset(0.U)
val EVENT1 = RW(19, 10).withReset(0.U)
val EVENT0 = RW(9, 0).withReset(0.U)
}

object OPTYPE extends CSREnum with WARLApply {
val OR = Value(0.U)
val AND = Value(1.U)
val XOR = Value(2.U)
val ADD = Value(4.U)

override def isLegal(enumeration: CSREnumType): Bool = enumeration.isOneOf(OR, AND, XOR, ADD)
}

trait HasOfFromPerfCntBundle { self: CSRModule[_] =>
val ofFromPerfCnt = IO(Input(Bool()))
}

trait HasMipToAlias { self: CSRModule[_] =>
val mipAlias = Output(new MipBundle)
}
Expand Down
43 changes: 31 additions & 12 deletions src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -652,7 +652,11 @@ class NewCSR(implicit val p: Parameters) extends Module
}
mod match {
case m: HasMhpmeventOfBundle =>
m.ofVec := VecInit(mhpmevents.map(event => event.rdata.head(1).asBool)).asUInt //todo：fix
m.ofVec := VecInit(mhpmevents.map{ event =>
val mhpmevent = Wire(new MhpmeventBundle)
mhpmevent := event.rdata
mhpmevent.OF.asBool
}).asUInt
m.privState := privState
m.mcounteren := mcounteren.rdata
m.hcounteren := hcounteren.rdata
Expand Down Expand Up @@ -806,7 +810,6 @@ class NewCSR(implicit val p: Parameters) extends Module
// perf
val addrInPerfCnt = (wenLegal || ren) && (
(addr >= CSRs.mcycle.U) && (addr <= CSRs.mhpmcounter31.U) ||
(addr === mcountinhibit.addr.U) ||
(addr >= CSRs.cycle.U) && (addr <= CSRs.hpmcounter31.U) ||
Cat(aiaSkipCSRs.map(_.addr.U === addr)).orR
)
Expand Down Expand Up @@ -1077,28 +1080,23 @@ class NewCSR(implicit val p: Parameters) extends Module
* perf_begin
* perf number: 29 (frontend 8, ctrlblock 8, memblock 8, huancun 5)
*/
// tmp: mhpmevents is wrapper of perfEvents, read/write/update mhpmevents -> read/write/update perfEvents
val csrevents = perfEvents.slice(24, 29)
val csrevents = mhpmevents.slice(24, 29).map(_.rdata)

val hcEvents = Wire(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent))
for (i <- 0 until numPCntHc * coreParams.L2NBanks) {
hcEvents(i) := io.perf.perfEventsHc(i)
}

val hpmHc = HPerfMonitor(csrevents, hcEvents)

val privState1H = Cat(privState.isModeM, privState.isModeHS, privState.isModeHU, privState.isModeVS, privState.isModeVU)
val countingEn = RegInit(0.U.asTypeOf(Vec(perfCntNum, Bool())))
for (i <-0 until perfCntNum) {
countingEn(i) := ((~mhpmevents(i).rdata(62, 58)).asUInt & privState1H).orR
}
val allPerfEvents = io.perf.perfEventsFrontend ++
io.perf.perfEventsBackend ++
io.perf.perfEventsLsu ++
hpmHc.getPerf

val countingEn = RegInit(0.U.asTypeOf(Vec(perfCntNum, Bool())))
val ofFromPerfCntVec = Wire(Vec(perfCntNum, Bool()))
val lcofiReqVec = Wire(Vec(perfCntNum, Bool()))

for(i <- 0 until perfCntNum) {
mhpmcounters(i) match {
case m: HasPerfCounterBundle =>
Expand All @@ -1107,8 +1105,22 @@ class NewCSR(implicit val p: Parameters) extends Module
ofFromPerfCntVec(i) := m.toMhpmeventOF
case _ =>
}
perfEvents(i) := Mux(mhpmevents(i).w.wen, wdata, (perfEvents(i).head(1).asBool || ofFromPerfCntVec(i)) ## perfEvents(i).tail(1))
lcofiReqVec(i) := ofFromPerfCntVec(i) && !mhpmevents(i).rdata.head(1)

mhpmevents(i) match {
case m: HasOfFromPerfCntBundle =>
m.ofFromPerfCnt := ofFromPerfCntVec(i)
case _ =>
}

val mhpmevent = Wire(new MhpmeventBundle)
mhpmevent := mhpmevents(i).rdata
lcofiReqVec(i) := ofFromPerfCntVec(i) && !mhpmevent.OF.asBool

countingEn(i) := (privState.isModeM && !mhpmevent.MINH) ||
(privState.isModeHS && !mhpmevent.SINH) ||
(privState.isModeHU && !mhpmevent.UINH) ||
(privState.isModeVS && !mhpmevent.VSINH) ||
(privState.isModeVU && !mhpmevent.VUINH)
}

val lcofiReq = lcofiReqVec.asUInt.orR
Expand Down Expand Up @@ -1431,6 +1443,13 @@ class NewCSR(implicit val p: Parameters) extends Module
diffNonRegInterruptPendingEvent.platformIRPVstip := sstcIRGen.o.VSTIP
diffNonRegInterruptPendingEvent.localCounterOverflowInterruptReq := mip.regOut.LCOFIP.asBool

val diffMhpmeventOverflowEvent = DifftestModule(new DiffMhpmeventOverflowEvent)
diffMhpmeventOverflowEvent.coreid := hartId
diffMhpmeventOverflowEvent.valid := Cat(mhpmevents.zipWithIndex.map{ case (event, i) =>
!ofFromPerfCntVec(i) && RegNext(ofFromPerfCntVec(i)) || ofFromPerfCntVec(i) && !RegNext(ofFromPerfCntVec(i))
}).orR
diffMhpmeventOverflowEvent.mhpmeventOverflow := VecInit(mhpmevents.map(_.regOut.asInstanceOf[MhpmeventBundle].OF.asBool)).asUInt

}
}

Expand Down
10 changes: 4 additions & 6 deletions src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -154,13 +154,11 @@ trait SupervisorLevel { self: NewCSR with MachineLevel =>
override val len: Int = 32
val OFVEC = RO(31, 3).withReset(0.U)
}) with HasMhpmeventOfBundle {
reg.OFVEC := ofVec
regOut.OFVEC := Mux1H(Seq(
privState.isModeM -> reg.OFVEC.asUInt,
privState.isModeHS -> (mcounteren.HPM.asUInt & reg.OFVEC.asUInt),
privState.isModeVS -> (mcounteren.HPM.asUInt & hcounteren.HPM.asUInt & reg.OFVEC.asUInt),
)
)
privState.isModeM -> ofVec,
privState.isModeHS -> (mcounteren.HPM.asUInt & ofVec),
privState.isModeVS -> (mcounteren.HPM.asUInt & hcounteren.HPM.asUInt & ofVec),
))
}).setAddr(CSRs.scountovf)

val sstateen0 = Module(new CSRModule("Sstateen", new SstateenBundle0) with HasStateen0Bundle {
Expand Down
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