fix(csr): add difftest of mhpmevent overflow to diff csr mhpmeventn

* Count overflow only from hardware incrementes of counter registers
* Through XiangShan->difftest->NEMU, to make NEMU get mhpmevent.of

src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala

@@ -787,7 +787,6 @@ class NewCSR(implicit val p: Parameters) extends Module
   // perf
   val addrInPerfCnt = (wenLegal || ren) && (
     (addr >= CSRs.mcycle.U) && (addr <= CSRs.mhpmcounter31.U) ||
-    (addr === mcountinhibit.addr.U) ||
     (addr >= CSRs.cycle.U) && (addr <= CSRs.hpmcounter31.U) ||
     Cat(aiaSkipCSRs.map(_.addr.U === addr)).orR
   )
@@ -1416,6 +1415,13 @@ class NewCSR(implicit val p: Parameters) extends Module
     diffNonRegInterruptPendingEvent.platformIRPVstip := sstcIRGen.o.VSTIP
     diffNonRegInterruptPendingEvent.localCounterOverflowInterruptReq  := mip.regOut.LCOFIP.asBool
 
+    val diffMhpmeventOverflowEvent = DifftestModule(new DiffMhpmeventOverflowEvent)
+    diffMhpmeventOverflowEvent.coreid := hartId
+    diffMhpmeventOverflowEvent.valid  := Cat(mhpmevents.zipWithIndex.map{ case (event, i) =>
+      !ofFromPerfCntVec(i) && RegNext(ofFromPerfCntVec(i)) || ofFromPerfCntVec(i) && !RegNext(ofFromPerfCntVec(i))
+    }).orR
+    diffMhpmeventOverflowEvent.mhpmeventOverflow := VecInit(mhpmevents.map(_.regOut.asInstanceOf[MhpmeventBundle].OF.asBool)).asUInt
+
   }
 }