fix(dbltrp): trap info update in raise_intr (#596)

* add trapInfo buffer to save tval/tval2/tinst in mmu/amo/paddr * assign tval/tval2/tinst to xtval/tval2/tinst according to xedeleg/xideleg in raise_intr * allow software to clear nmie as we init nmie to 1
OpenXiangShan · Oct 25, 2024 · 8aec46a · 8aec46a
1 parent 8f0720f
commit 8aec46a
Show file tree

Hide file tree

Showing 7 changed files with 100 additions and 57 deletions.
diff --git a/src/isa/riscv64/instr/rva/amo.c b/src/isa/riscv64/instr/rva/amo.c
@@ -18,6 +18,7 @@
 #include <memory/paddr.h>
 #include <rtl/rtl.h>
 #include "../local-include/intr.h"
+#include "../local-include/trapinfo.h"
 #include "cpu/difftest.h"
 __attribute__((cold))
 def_rtl(amo_slow_path, rtlreg_t *dest, const rtlreg_t *src1, const rtlreg_t *src2) {
@@ -64,7 +65,7 @@ def_rtl(amo_slow_path, rtlreg_t *dest, const rtlreg_t *src1, const rtlreg_t *src
       // Even if scInvalid, SAF (if raised) also needs to be reported
       // Check address space range and pmp
       if (!in_pmem(paddr) || !isa_pmp_check_permission(paddr, width, MEM_TYPE_WRITE, cpu.mode)) {
-        INTR_TVAL_REG(EX_SAF) = *src1;
+        trapInfo.tval = *src1;
         longjmp_exception(EX_SAF);
       }
     }

diff --git a/src/isa/riscv64/local-include/intr.h b/src/isa/riscv64/local-include/intr.h
@@ -90,13 +90,7 @@ word_t raise_intr(word_t NO, vaddr_t epc);
 #define return_on_mem_ex() do { if (cpu.mem_exception != MEM_OK) return; } while (0)
 bool intr_deleg_S(word_t exceptionNO);
 bool intr_deleg_VS(word_t exceptionNO);
-#ifdef CONFIG_RVH
-#define INTR_TVAL_REG(ex) (*((intr_deleg_VS(ex)) ? (word_t *)vstval :(intr_deleg_S(ex)) ? (word_t *)stval : (word_t *)mtval))
-#define INTR_TVAL2_REG(ex) (*((intr_deleg_S(ex)) ? (word_t *)htval : (word_t *)mtval2))
-#define INTR_TINST_REG(ex) (*((intr_deleg_S(ex)) ? (word_t *)htinst : (word_t *)mtinst))
-#else
-#define INTR_TVAL_REG(ex) (*((intr_deleg_S(ex)) ? (word_t *)stval : (word_t *)mtval))
-#endif
+
 
 #ifdef CONFIG_RVH
 #define SELECT_DUT_INTR_TVAL_REG(ex) ((intr_deleg_VS(ex)) ? (word_t)cpu.execution_guide.vstval :(intr_deleg_S(ex)) ? (word_t)cpu.execution_guide.stval : (word_t)cpu.execution_guide.mtval)

diff --git a/src/isa/riscv64/local-include/trapinfo.h b/src/isa/riscv64/local-include/trapinfo.h
@@ -0,0 +1,32 @@
+/***************************************************************************************
+* Copyright (c) 2014-2021 Zihao Yu, Nanjing University
+* Copyright (c) 2020-2022 Institute of Computing Technology, Chinese Academy of Sciences
+*
+* NEMU is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*          http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+*
+* See the Mulan PSL v2 for more details.
+***************************************************************************************/
+
+#ifndef __TRAPINFO_H__
+#define __TRAPINFO_H__
+
+#include "common.h"
+
+typedef struct {
+    word_t tval;
+    word_t tval2;
+    word_t tinst;
+} trap_info_t;
+
+extern trap_info_t trapInfo;
+void clear_trapinfo();
+
+
+#endif // __TRAPINFO_H__
diff --git a/src/isa/riscv64/system/intr.c b/src/isa/riscv64/system/intr.c
@@ -19,9 +19,11 @@
 #include "../local-include/trigger.h"
 #include "../local-include/csr.h"
 #include "../local-include/intr.h"
+#include "../local-include/trapinfo.h"
 
 void update_mmu_state();
 
+trap_info_t trapInfo = {};
 
 #ifdef CONFIG_RVH
 bool intr_deleg_S(word_t exceptionNO) {
@@ -47,6 +49,10 @@ bool intr_deleg_S(word_t exceptionNO) {
 }
 #endif
 
+void clear_trapinfo(){
+  memset(&trapInfo, 0, sizeof(trap_info_t));
+}
+
 static word_t get_trap_pc(word_t xtvec, word_t xcause) {
   word_t base = (xtvec >> 2) << 2;
   word_t mode = (xtvec & 0x1); // bit 1 is reserved, dont care here.
@@ -100,6 +106,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
     case EX_SPF: difftest_skip_dut(1, 2); break;
   }
 #endif
+  MUXDEF(CONFIG_RV_SMRNMI,Assert( mnstatus->nmie, "critical error: trap when nmie close"), );
   bool isNMI = MUXDEF(CONFIG_RV_SMRNMI, cpu.hasNMI && (NO & INTR_BIT), false);
   bool delegS = intr_deleg_S(NO);
   bool delegM = !delegS && !isNMI;
@@ -129,6 +136,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
     vsstatus->spie = vsstatus->sie;
     vsstatus->sie = 0;
     vsstatus->sdt = MUXDEF(CONFIG_RV_SSDBLTRP, henvcfg->dte && menvcfg->dte, 0);
+    vstval->val = trapInfo.tval;
     // vsstatus->spp = cpu.mode;
     // vsstatus->spie = vsstatus->sie;
     // vsstatus->sie = 0;
@@ -159,6 +167,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
     cpu.v = 1;
     cpu.mode = MODE_S;
     update_mmu_state();
+    clear_trapinfo();
     return get_trap_pc(vstvec->val, vscause->val);
   }
   else if(delegS && !s_EX_DT){
@@ -181,6 +190,9 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
     mstatus->spie = mstatus->sie;
     mstatus->sie = 0;
     mstatus->sdt = MUXDEF(CONFIG_RV_SSDBLTRP, menvcfg->dte, 0);
+    MUXDEF(CONFIG_RVH, htval->val = trapInfo.tval2;, )
+    MUXDEF(CONFIG_RVH, htinst->val = trapInfo.tinst;, )
+    stval->val = trapInfo.tval;
     switch (NO) {
       case EX_IPF: case EX_LPF: case EX_SPF:
       case EX_LAM: case EX_SAM:
@@ -221,6 +233,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
     // 18.6.3. Transformed Instruction or Pseudoinstruction for mtinst or htinst.
     cpu.mode = MODE_S;
     update_mmu_state();
+    clear_trapinfo();
     return get_trap_pc(stvec->val, scause->val);
     // return stvec->val;
   } else if((delegM || vs_EX_DT || s_EX_DT) && !m_EX_DT){
@@ -236,6 +249,9 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
     mstatus->mpp = cpu.mode;
     mstatus->mpie = mstatus->mie;
     mstatus->mie = 0;
+    mtval->val = trapInfo.tval;
+    MUXDEF(CONFIG_RVH, mtval2->val = trapInfo.tval2;, )
+    MUXDEF(CONFIG_RVH, mtinst->val = trapInfo.tinst;, )
     switch (NO) {
       case EX_IPF: case EX_LPF: case EX_SPF:
       case EX_LAM: case EX_SAM:
@@ -279,6 +295,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
 #endif //CONFIG_RV_SSDBLTRP
     cpu.mode = MODE_M;
     update_mmu_state();
+    clear_trapinfo();
     return get_trap_pc(mtvec->val, mcause->val);
   }
 #ifdef CONFIG_RV_SMRNMI
@@ -292,6 +309,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
     mncause->val = NO;
     cpu.mode = MODE_M;
     update_mmu_state();
+    clear_trapinfo();
     return get_trap_pc(mtvec->val, mncause->val);
   }
 #endif //CONFIG_RV_SMRNMI