feat(dev-zihintpause): add support for pause (#622)

* decode pause to FENCE with pred=W, succ=0, fm=0, rd=x0, rs1=x0 * Currently, FENCE has no side effects.
OpenXiangShan · Nov 1, 2024 · 63941ad · 63941ad
1 parent ab7e079
commit 63941ad
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diff --git a/configs/riscv64-dual-xs-ref_defconfig b/configs/riscv64-dual-xs-ref_defconfig
@@ -41,6 +41,7 @@ CONFIG_RV_SSDBLTRP=y
 CONFIG_NMIE_INIT=y
 CONFIG_RV_ZICNTR=y
 CONFIG_RV_CSR_TIME=y
+CONFIG_RV_ZIHINTPAUSE=y
 CONFIG_RV_ZIHPM=y
 CONFIG_RV_CSR_MCOUNTINHIBIT=y
 CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR=y
@@ -69,6 +70,7 @@ CONFIG_USE_XS_ARCH_CSRS=y
 CONFIG_RVV_AGNOSTIC=y
 CONFIG_RV_ZCMOP=y
 CONFIG_RV_ZIMOP=y
+CONFIG_RV_ZCB=y
 # end of ISA-dependent Options for riscv64
 
 CONFIG_ENGINE_INTERPRETER=y

diff --git a/configs/riscv64-xs-ref_defconfig b/configs/riscv64-xs-ref_defconfig
@@ -41,6 +41,7 @@ CONFIG_RV_SSDBLTRP=y
 CONFIG_NMIE_INIT=y
 CONFIG_RV_ZICNTR=y
 CONFIG_RV_CSR_TIME=y
+CONFIG_RV_ZIHINTPAUSE=y
 CONFIG_RV_ZIHPM=y
 CONFIG_RV_CSR_MCOUNTINHIBIT=y
 CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR=y

diff --git a/configs/riscv64-xs_defconfig b/configs/riscv64-xs_defconfig
@@ -39,6 +39,7 @@ CONFIG_RV_SSDBLTRP=y
 CONFIG_NMIE_INIT=y
 CONFIG_RV_ZICNTR=y
 CONFIG_RV_CSR_TIME=y
+CONFIG_RV_ZIHINTPAUSE=y
 CONFIG_RV_ZIHPM=y
 CONFIG_RV_CSR_MCOUNTINHIBIT=y
 CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR=y

diff --git a/src/isa/riscv64/Kconfig b/src/isa/riscv64/Kconfig
@@ -112,6 +112,11 @@ config MDT_INIT
   bool "Init mstatus.mdt to 1"
   depends on RV_SMDBLTRP
   default n
+  help
+    This config control the init value of mstatus.mdt. As software not support
+    Smdbltrp yet, the default value of this config is set to n. After software
+    support, this config should be open.
+
 
 config RV_SSDBLTRP
   bool "RISC-V S-Mode Double Trap Extension"
@@ -122,6 +127,10 @@ config NMIE_INIT
   bool "Init mnstatus.nmie to 1 and allow software to clear"
   depends on RV_SMRNMI
   default y
+  help
+    This config control the init value of mnstatus.nmie and whether allow software
+    to clear. As software not support Smrnmi yet, the default value of this config
+    is set to y. After software support, this config should be close.
 
 menuconfig RV_ZICNTR
   bool "RISC-V Zicntr Extensions for Base Counters and Timers, v2.0"
@@ -146,6 +155,10 @@ config RV_CSR_TIME
 
 endif # RV_ZICNTR
 
+config RV_ZIHINTPAUSE
+    bool "RISC-V Zihintpause for Pause Hint, v2.0"
+    default y
+
 config RV_ZIHPM
   bool "RISC-V Zihpm Extensions for Hardware Performance Counters, v2.0" 
   default y

diff --git a/src/isa/riscv64/include/isa-all-instr.h b/src/isa/riscv64/include/isa-all-instr.h
@@ -329,8 +329,16 @@
 #define ZCB_INSTR_TERNARY(f)
 #endif // CONFIG_RV_ZCB
 
+#ifdef CONFIG_RV_ZIHINTPAUSE
+#define ZIHINTPAUSE_INSTR_NULLARY(f) \
+  f(pause)
+#else
+#define ZIHINTPAUSE_INSTR_NULLARY(f)
+#endif //CONFIG_RV_ZIHINTPAUSE
+
 #define INSTR_NULLARY(f) \
   f(inv) f(rt_inv) f(nemu_trap) \
+  ZIHINTPAUSE_INSTR_NULLARY(f) \
   f(fence_i) f(fence) \
   SYS_INSTR_NULLARY(f)   \
   SYS_NMI_NULLARY(f) \

diff --git a/src/isa/riscv64/instr/priv/exec.h b/src/isa/riscv64/instr/priv/exec.h
@@ -64,7 +64,7 @@ MAP(RVH_ST_INST_LIST, def_hst_template)
 #define SYS_INSTR_LIST(f) \
   f(csrrw)  f(csrrs)  f(csrrc) f(csrrwi) f(csrrsi) f(csrrci) \
   SYS_MNINSTR_LIST(f)       \
-  f(ecall)  f(ebreak) f(mret)  f(mnret) f(sret)  f(sfence_vma) f(wfi)
+  f(ecall)  f(ebreak) f(mret)  f(sret)  f(sfence_vma) f(wfi)
 #endif
 
 MAP(SYS_INSTR_LIST, def_SYS_EHelper)

diff --git a/src/isa/riscv64/instr/rvi/decode.h b/src/isa/riscv64/instr/rvi/decode.h
@@ -317,6 +317,9 @@ def_THelper(jalr_dispatch) {
 }
 
 def_THelper(mem_fence) {
+#ifdef CONFIG_RV_ZIHINTPAUSE
+  def_INSTR_TAB("0000000 10000 00000 000 00000 00011 11", pause);
+#endif //CONFIG_RV_ZIHINTPAUSE
   def_INSTR_TAB("??????? ????? ????? 000 ????? ????? ??", fence);
   def_INSTR_TAB("??????? ????? ????? 001 ????? ????? ??", fence_i);
   return EXEC_ID_inv;

diff --git a/src/isa/riscv64/instr/rvi/fence.h b/src/isa/riscv64/instr/rvi/fence.h
@@ -22,3 +22,9 @@ def_EHelper(fence_i) {
 def_EHelper(fence) {
   IFNDEF(CONFIG_DIFFTEST_REF_NEMU, difftest_skip_dut(1, 2));
 }
+
+#ifdef CONFIG_RV_ZIHINTPAUSE
+def_EHelper(pause) {
+  IFNDEF(CONFIG_DIFFTEST_REF_NEMU, difftest_skip_dut(1, 2));
+}
+#endif //CONFIG_RV_ZIHINTPAUSE