fix(fs, vs): fix check fs/vs when executing float/vector instr (#621)

Including fldst instrucitons under RVC extension.
OpenXiangShan · Oct 30, 2024 · 404753f · 404753f
1 parent 7e6edfa
commit 404753f
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Showing 3 changed files with 26 additions and 2 deletions.
diff --git a/src/isa/riscv64/instr/fp.c b/src/isa/riscv64/instr/fp.c
@@ -32,7 +32,19 @@ void fp_update_rm_cache(uint32_t rm) {
 }
 
 bool fp_enable() {
-  return MUXDEF(CONFIG_MODE_USER, true, mstatus->fs != 0);
+#ifdef CONFIG_MODE_USER
+  return true;
+#else // !CONFIG_MODE_USER
+  if (mstatus->fs == 0) {
+    return false;
+  }
+#ifdef CONFIG_RVH
+  if (cpu.v && vsstatus->fs == 0) {
+    return false;
+  }
+#endif // CONFIG_RVH
+  return true;
+#endif // CONFIG_MODE_USER
 }
 
 void fp_set_dirty() {

diff --git a/src/isa/riscv64/instr/rvc/decode.h b/src/isa/riscv64/instr/rvc/decode.h
@@ -431,6 +431,7 @@ def_THelper(c_ldst) {
 
 def_THelper(c_fldst) {
 #ifndef CONFIG_FPU_NONE
+  if (!fp_enable()) return table_rt_inv(s);
   int mmu_mode = isa_mmu_state();
   if (mmu_mode == MMU_DIRECT) {
     def_INSTR_TAB("001 ??? ??? ?? ??? ??", fld);

diff --git a/src/isa/riscv64/instr/vp.c b/src/isa/riscv64/instr/vp.c
@@ -20,8 +20,19 @@
 #include <cpu/cpu.h>
 
 bool vp_enable() {
+#ifdef CONFIG_MODE_USER
   return true;
-  //return MUXDEF(CONFIG_MODE_USER, true, mstatus->vs != 0);
+#else // !CONFIG_MODE_USER
+  if (mstatus->vs == 0) {
+    return false;
+  }
+#ifdef CONFIG_RVH
+  if (cpu.v && vsstatus->vs == 0) {
+    return false;
+  }
+#endif // CONFIG_RVH
+  return true;
+#endif // CONFIG_MODE_USER
 }
 
 void vp_set_dirty() {