feat(trigger): implement icount, itrigger and etrigger triggers.

This patch remove timing use in trigger mcontrol6. For mcontrol6 you can't request a timing. Default to before since that's most useful to the user. Also fixed and optimized the read and write operations for the CSR related to triggers.
OpenXiangShan · Nov 1, 2024 · 303d462 · 303d462
1 parent 861f8d3
commit 303d462
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Showing 26 changed files with 400 additions and 164 deletions.
diff --git a/configs/riscv64-dual-xs-ref_defconfig b/configs/riscv64-dual-xs-ref_defconfig
@@ -28,6 +28,10 @@ CONFIG_RV_DEBUG=y
 CONFIG_RVH=y
 # CONFIG_RV_SDEXT is not set
 CONFIG_RV_SDTRIG=y
+CONFIG_TDATA1_MCONTROL6=y
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 CONFIG_TRIGGER_NUM=4
 # CONFIG_SDTRIG_EXTRA is not set
 CONFIG_RV_AIA=y

diff --git a/configs/riscv64-gem5-multicore-ref_defconfig b/configs/riscv64-gem5-multicore-ref_defconfig
@@ -26,6 +26,10 @@ CONFIG_RV_ZIHPM=n
 
 # CONFIG_RV_SDEXT is not set
 # CONFIG_RV_SDTRIG is not set
+# CONFIG_TDATA1_MCONTROL6 is not set
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 # CONFIG_RV_PMP_ENTRY_0 is not set
 CONFIG_RV_PMP_ENTRY_16=y
 # CONFIG_RV_PMP_ENTRY_64 is not set

diff --git a/configs/riscv64-gem5-ref_defconfig b/configs/riscv64-gem5-ref_defconfig
@@ -27,6 +27,10 @@ CONFIG_RV_ZIHPM=n
 
 # CONFIG_RV_SDEXT is not set
 # CONFIG_RV_SDTRIG is not set
+# CONFIG_TDATA1_MCONTROL6 is not set
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 # CONFIG_RV_PMP_ENTRY_0 is not set
 CONFIG_RV_PMP_ENTRY_16=y
 # CONFIG_RV_PMP_ENTRY_64 is not set

diff --git a/configs/riscv64-spm-ref-xs_defconfig b/configs/riscv64-spm-ref-xs_defconfig
@@ -22,6 +22,10 @@ CONFIG_RV_DEBUG=y
 # CONFIG_RVH is not set
 # CONFIG_RV_SDEXT is not set
 # CONFIG_RV_SDTRIG is not set
+# CONFIG_TDATA1_MCONTROL6 is not set
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 # CONFIG_RV_PMP_ENTRY_0 is not set
 CONFIG_RV_PMP_ENTRY_16=y
 # CONFIG_RV_PMP_ENTRY_64 is not set

diff --git a/configs/riscv64-spm-xs_defconfig b/configs/riscv64-spm-xs_defconfig
@@ -22,6 +22,10 @@ CONFIG_RV_DEBUG=y
 # CONFIG_RVH is not set
 # CONFIG_RV_SDEXT is not set
 # CONFIG_RV_SDTRIG is not set
+# CONFIG_TDATA1_MCONTROL6 is not set
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 # CONFIG_RV_PMP_ENTRY_0 is not set
 CONFIG_RV_PMP_ENTRY_16=y
 # CONFIG_RV_PMP_ENTRY_64 is not set

diff --git a/configs/riscv64-xs-cpt_defconfig b/configs/riscv64-xs-cpt_defconfig
@@ -28,6 +28,10 @@ CONFIG_RV_DEBUG=y
 CONFIG_RVH=y
 # CONFIG_RV_SDEXT is not set
 CONFIG_RV_SDTRIG=y
+CONFIG_TDATA1_MCONTROL6=y
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 CONFIG_TRIGGER_NUM=4
 # CONFIG_RV_AIA is not set
 # CONFIG_RV_SSTC is not set

diff --git a/configs/riscv64-xs-diff-spike-agnostic_defconfig b/configs/riscv64-xs-diff-spike-agnostic_defconfig
@@ -23,6 +23,10 @@ CONFIG_RV_DEBUG=y
 CONFIG_RVH=y
 # CONFIG_RV_SDEXT is not set
 CONFIG_RV_SDTRIG=y
+CONFIG_TDATA1_MCONTROL6=y
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 CONFIG_TRIGGER_NUM=4
 # CONFIG_RV_AIA is not set
 CONFIG_RV_ZICNTR=y

diff --git a/configs/riscv64-xs-diff-spike_defconfig b/configs/riscv64-xs-diff-spike_defconfig
@@ -28,6 +28,10 @@ CONFIG_RV_DEBUG=y
 CONFIG_RVH=y
 # CONFIG_RV_SDEXT is not set
 CONFIG_RV_SDTRIG=y
+CONFIG_TDATA1_MCONTROL6=y
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 CONFIG_TRIGGER_NUM=4
 # CONFIG_RV_AIA is not set
 # CONFIG_RV_SSTC is not set

diff --git a/configs/riscv64-xs-ref_defconfig b/configs/riscv64-xs-ref_defconfig
@@ -28,6 +28,10 @@ CONFIG_RV_DEBUG=y
 CONFIG_RVH=y
 # CONFIG_RV_SDEXT is not set
 CONFIG_RV_SDTRIG=y
+CONFIG_TDATA1_MCONTROL6=y
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 CONFIG_TRIGGER_NUM=4
 # CONFIG_SDTRIG_EXTRA is not set
 CONFIG_RV_AIA=y

diff --git a/configs/riscv64-xs-southlake-ref_defconfig b/configs/riscv64-xs-southlake-ref_defconfig
@@ -21,6 +21,10 @@ CONFIG_RVK=y
 CONFIG_RV_DEBUG=y
 CONFIG_RV_SDEXT=y
 CONFIG_RV_SDTRIG=y
+CONFIG_TDATA1_MCONTROL6=y
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 CONFIG_TRIGGER_NUM=10
 # CONFIG_RV_PMP_ENTRY_0 is not set
 CONFIG_RV_PMP_ENTRY_16=y

diff --git a/configs/riscv64-xs-spmem-ref_defconfig b/configs/riscv64-xs-spmem-ref_defconfig
@@ -22,6 +22,10 @@ CONFIG_RV_DEBUG=y
 CONFIG_RVH=y
 CONFIG_RV_SDEXT=y
 CONFIG_RV_SDTRIG=y
+CONFIG_TDATA1_MCONTROL6=y
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 CONFIG_TRIGGER_NUM=10
 # CONFIG_RV_PMP_ENTRY_0 is not set
 CONFIG_RV_PMP_ENTRY_16=y

diff --git a/configs/riscv64-xs-spmem-so-ref_defconfig b/configs/riscv64-xs-spmem-so-ref_defconfig
@@ -22,6 +22,10 @@ CONFIG_RV_DEBUG=y
 CONFIG_RVH=y
 CONFIG_RV_SDEXT=y
 CONFIG_RV_SDTRIG=y
+CONFIG_TDATA1_MCONTROL6=y
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 CONFIG_TRIGGER_NUM=10
 # CONFIG_RV_PMP_ENTRY_0 is not set
 CONFIG_RV_PMP_ENTRY_16=y

diff --git a/configs/riscv64-xs_defconfig b/configs/riscv64-xs_defconfig
@@ -28,6 +28,10 @@ CONFIG_RV_DEBUG=y
 CONFIG_RVH=y
 # CONFIG_RV_SDEXT is not set
 CONFIG_RV_SDTRIG=y
+CONFIG_TDATA1_MCONTROL6=y
+# CONFIG_TDATA1_ICOUNT is not set
+# CONFIG_TDATA1_ITRIGGER is not set
+# CONFIG_TDATA1_ETRIGGER is not set
 CONFIG_TRIGGER_NUM=4
 # CONFIG_SDTRIG_EXTRA is not set
 # CONFIG_RV_AIA is not set

diff --git a/src/cpu/cpu-exec.c b/src/cpu/cpu-exec.c
@@ -26,6 +26,7 @@
 #include <unistd.h>
 #include <generated/autoconf.h>
 #include <profiling/profiling_control.h>
+#include "../local-include/trigger.h"
 
 /* The assembly code of instructions executed is only output to the screen
  * when the number of instructions executed is less than this value.
@@ -672,15 +673,23 @@ void cpu_exec(uint64_t n) {
     if (cause == NEMU_EXEC_EXCEPTION) {
       Loge("Handle NEMU_EXEC_EXCEPTION");
       cause = 0;
+      IFDEF(CONFIG_TDATA1_ETRIGGER, trig_action_t action = check_triggers_etrigger(cpu.TM, g_ex_cause));
       cpu.pc = raise_intr(g_ex_cause, prev_s->pc);
       cpu.amo = false; // clean up
       IFDEF(CONFIG_PERF_OPT, tcache_handle_exception(cpu.pc));
+      IFDEF(CONFIG_TDATA1_ETRIGGER, trigger_handler(TRIG_TYPE_ETRIG, action, 0));
       IFDEF(CONFIG_SHARE, break);
     } else {
       word_t intr = MUXDEF(CONFIG_SHARE, INTR_EMPTY, isa_query_intr());
       if (intr != INTR_EMPTY) {
         Loge("NEMU raise intr");
+#ifdef CONFIG_TDATA1_ICOUNT
+        trig_action_t icount_action = check_triggers_icount(cpu.TM);
+        trigger_handler(TRIG_TYPE_ICOUNT, icount_action, 0);
+#endif // CONFIG_TDATA1_ICOUNT
+        IFDEF(CONFIG_TDATA1_ITRIGGER, trig_action_t itrigger_action = check_triggers_itrigger(cpu.TM, intr));
         cpu.pc = raise_intr(intr, cpu.pc);
+        IFDEF(CONFIG_TDATA1_ITRIGGER, trigger_handler(TRIG_TYPE_ITRIG, itrigger_action, 0));
         IFDEF(CONFIG_DIFFTEST, ref_difftest_raise_intr(intr));
         IFDEF(CONFIG_PERF_OPT, tcache_handle_exception(cpu.pc));
       }

diff --git a/src/isa/riscv64/Kconfig b/src/isa/riscv64/Kconfig
@@ -67,6 +67,26 @@ config RV_SDTRIG
   depends on RV_DEBUG
   default n
 
+config TDATA1_MCONTROL6
+  bool "TDATA1 Support mcontrol6 Type of Trigger"
+  depends on RV_SDTRIG
+  default n
+
+config TDATA1_ICOUNT
+  bool "TDATA1 Support icount Type of Trigger"
+  depends on RV_SDTRIG
+  default n
+
+config TDATA1_ITRIGGER
+  bool "TDATA1 Support itrigger Type of Trigger"
+  depends on RV_SDTRIG
+  default n
+
+config TDATA1_ETRIGGER
+  bool "TDATA1 Support etrigger Type of Trigger"
+  depends on RV_SDTRIG
+  default n
+
 config TRIGGER_NUM
   int "Number of supported triggers"
   depends on RV_SDTRIG

diff --git a/src/isa/riscv64/difftest/ref.c b/src/isa/riscv64/difftest/ref.c
@@ -20,6 +20,7 @@
 #include <difftest.h>
 #include "../local-include/intr.h"
 #include "../local-include/csr.h"
+#include "../local-include/trigger.h"
 #include <generated/autoconf.h>
 #include <stdlib.h>
 
@@ -91,7 +92,7 @@ void csr_prepare() {
 #endif
 #ifdef CONFIG_RV_SDTRIG
   cpu.tselect  = tselect->val;
-  cpu.tdata1   = tdata1->val;
+  cpu.tdata1   = get_tdata1(cpu.TM);
   cpu.tinfo    = tinfo->val;
 #endif // CONFIG_RV_SDTRIG
 #ifndef CONFIG_FPU_NONE
@@ -153,7 +154,7 @@ void csr_writeback() {
 #endif
 #ifdef CONFIG_RV_SDTRIG
   tselect->val  = cpu.tselect;
-  tdata1->val   = cpu.tdata1;
+  cpu.TM->triggers[tselect->val].tdata1.val = cpu.tdata1; // update alias tdata1 to trigger module
   tinfo->val    = cpu.tinfo;
 #endif // CONFIG_RV_SDTRIG
 #ifndef CONFIG_FPU_NONE
@@ -280,8 +281,16 @@ void isa_difftest_raise_intr(word_t NO, uint64_t restore_count) {
 void isa_difftest_raise_intr(word_t NO) {
 #endif // CONFIG_LIGHTQS
   //ramcmp();
+#ifdef CONFIG_TDATA1_ICOUNT
+  trig_action_t icount_action = check_triggers_icount(cpu.TM);
+  trigger_handler(TRIG_TYPE_ICOUNT, icount_action, 0);
+#endif // CONFIG_TDATA1_ICOUNT
+  IFDEF(CONFIG_TDATA1_ITRIGGER, trig_action_t itrigger_action = check_triggers_itrigger(cpu.TM, NO));
+
   cpu.pc = raise_intr(NO, cpu.pc);
 
+  IFDEF(CONFIG_TDATA1_ITRIGGER, trigger_handler(TRIG_TYPE_ITRIG, itrigger_action, 0));
+
 #ifdef CONFIG_LIGHTQS
   // after processing, take another snapshot
   // FIXME: update spec_log_begin

diff --git a/src/isa/riscv64/instr/decode.c b/src/isa/riscv64/instr/decode.c
@@ -105,13 +105,14 @@ def_THelper(main) {
 int isa_fetch_decode(Decode *s) {
   int idx = EXEC_ID_inv;
 
-#ifdef CONFIG_RV_SDTRIG
-  trig_action_t action = TRIG_ACTION_NONE;
-  if (cpu.TM->check_timings.bf) {
-    action = tm_check_hit(cpu.TM, TRIG_OP_EXECUTE, s->pc, TRIGGER_NO_VALUE);
-  }
-  trigger_handler(action, s->pc);
-#endif
+#ifdef CONFIG_TDATA1_ICOUNT
+  trig_action_t icount_action = check_triggers_icount(cpu.TM);
+  trigger_handler(TRIG_TYPE_ICOUNT, icount_action, 0);
+#endif // CONFIG_TDATA1_ICOUNT
+#ifdef CONFIG_TDATA1_MCONTROL6
+  trig_action_t mcontrol6_action = check_triggers_mcontrol6(cpu.TM, TRIG_OP_EXECUTE, s->pc, TRIGGER_NO_VALUE);
+  trigger_handler(TRIG_TYPE_MCONTROL6, mcontrol6_action, s->pc);
+#endif // CONFIG_TDATA1_MCONTROL6
 
   s->isa.instr.val = instr_fetch(&s->snpc, 2);
   if (s->isa.instr.r.opcode1_0 != 0x3) {
@@ -127,13 +128,6 @@ int isa_fetch_decode(Decode *s) {
     idx = table_main(s);
   }
 
-#ifdef CONFIG_RV_SDTRIG
-  if (cpu.TM->check_timings.af) {
-    action = tm_check_hit(cpu.TM, (trig_op_t)(TRIG_OP_EXECUTE | TRIG_OP_TIMING), s->pc, s->isa.instr.val);
-  }
-  trigger_handler(action, s->pc);
-#endif
-
   s->type = INSTR_TYPE_N;
   switch (idx) {
     case EXEC_ID_c_j: case EXEC_ID_p_jal: case EXEC_ID_jal:

diff --git a/src/isa/riscv64/instr/rva/amo.c b/src/isa/riscv64/instr/rva/amo.c
@@ -26,14 +26,17 @@ def_rtl(amo_slow_path, rtlreg_t *dest, const rtlreg_t *src1, const rtlreg_t *src
   uint32_t funct5 = s->isa.instr.r.funct7 >> 2;
   int width = s->isa.instr.r.funct3 & 1 ? 8 : 4;
 
+#ifdef CONFIG_TDATA1_MCONTROL6
+  trig_action_t action = TRIG_ACTION_NONE;
   if (funct5 == 0b00010) { // lr
-    IFDEF(CONFIG_RV_SDTRIG, trigger_check(cpu.TM->check_timings.br, cpu.TM, TRIG_OP_LOAD, *src1, TRIGGER_NO_VALUE));
+    action = check_triggers_mcontrol6(cpu.TM, TRIG_OP_LOAD, *src1, TRIGGER_NO_VALUE); trigger_handler(TRIG_TYPE_MCONTROL6, action, *src1);
   } else if(funct5 == 0b00011) { // sc
-    IFDEF(CONFIG_RV_SDTRIG, trigger_check(cpu.TM->check_timings.bw, cpu.TM, TRIG_OP_STORE, *src1, TRIGGER_NO_VALUE));
-  } else{ // amo
-    IFDEF(CONFIG_RV_SDTRIG, trigger_check(cpu.TM->check_timings.br, cpu.TM, TRIG_OP_LOAD, *src1, TRIGGER_NO_VALUE));
-    IFDEF(CONFIG_RV_SDTRIG, trigger_check(cpu.TM->check_timings.bw, cpu.TM, TRIG_OP_STORE, *src1, TRIGGER_NO_VALUE));
+    action = check_triggers_mcontrol6(cpu.TM, TRIG_OP_STORE, *src1, TRIGGER_NO_VALUE); trigger_handler(TRIG_TYPE_MCONTROL6, action, *src1);
+  } else { // amo
+    action = check_triggers_mcontrol6(cpu.TM, TRIG_OP_LOAD, *src1, TRIGGER_NO_VALUE); trigger_handler(TRIG_TYPE_MCONTROL6, action, *src1);
+    action = check_triggers_mcontrol6(cpu.TM, TRIG_OP_STORE, *src1, TRIGGER_NO_VALUE); trigger_handler(TRIG_TYPE_MCONTROL6, action, *src1);
   }
+#endif // CONFIG_TDATA1_MCONTROL6
 
   // AMO does not support misalign operation
   // So check misalign before real memory access

diff --git a/src/isa/riscv64/instr/rvi/exec.h b/src/isa/riscv64/instr/rvi/exec.h
@@ -15,7 +15,7 @@
 
 #include "compute.h"
 
-#ifndef CONFIG_RV_SDTRIG
+#ifndef CONFIG_TDATA1_MCONTROL6
 #include "ldst.h"
 #else
 #include "ldst_trig.h"

diff --git a/src/isa/riscv64/instr/rvi/ldst_trig.h b/src/isa/riscv64/instr/rvi/ldst_trig.h
@@ -2,27 +2,18 @@
   def_EHelper(name) { \
     trig_action_t action = TRIG_ACTION_NONE; \
     const vaddr_t vaddr = *dsrc1 + id_src2->imm; \
-    if (cpu.TM->check_timings.br) { \
-      action = tm_check_hit(cpu.TM, TRIG_OP_LOAD, vaddr, TRIGGER_NO_VALUE); \
-    } \
-    trigger_handler(action, vaddr); \
+    action = check_triggers_mcontrol6(cpu.TM, TRIG_OP_LOAD, vaddr, TRIGGER_NO_VALUE); \
+    trigger_handler(TRIG_TYPE_MCONTROL6, action, vaddr); \
     concat(rtl_, rtl_instr) (s, ddest, dsrc1, id_src2->imm, width, mmu_mode); \
-    const rtlreg_t data = *ddest; \
-    if (cpu.TM->check_timings.ar) { \
-      action = tm_check_hit(cpu.TM, (trig_op_t)(TRIG_OP_LOAD | TRIG_OP_TIMING), vaddr, data); \
-    } \
-    trigger_handler(action, vaddr); \
   }
 
 #define def_st_template_with_trigger(name, rtl_instr, width, mmu_mode) \
   def_EHelper(name) { \
     trig_action_t action = TRIG_ACTION_NONE; \
     const vaddr_t vaddr = *dsrc1 + id_src2->imm; \
     const word_t data = *ddest; \
-    if (cpu.TM->check_timings.bw) { \
-      action = tm_check_hit(cpu.TM, TRIG_OP_STORE, vaddr, data); \
-    } \
-    trigger_handler(action, vaddr); \
+    action = check_triggers_mcontrol6(cpu.TM, TRIG_OP_STORE, vaddr, data); \
+    trigger_handler(TRIG_TYPE_MCONTROL6, action, vaddr); \
     concat(rtl_, rtl_instr) (s, ddest, dsrc1, id_src2->imm, width, mmu_mode); \
   }