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SPI Master-Slave Communication System

Project Description

This project involves the design and implementation of an SPI (Serial Peripheral Interface) Master-Slave communication system using Verilog. The SPI master module is capable of interfacing with multiple slave devices, making it suitable for a variety of embedded systems applications, including sensor interfacing and memory communication.

Features

  • SPI Master module implementation in Verilog
  • Supports communication with multiple slave devices using chip select signals
  • State machine design for managing data transfer and clock generation
  • Comprehensive testbench for simulation and verification
  • FPGA implementation for hardware validation

Pin Diagram

spi protocol

SPI Master

Signal Direction Description
clk Input System clock
rst Input Reset signal
data_in Input Data to be sent via SPI
start Input Start signal to initiate SPI
cs Input Chip select signals for slaves
spi_clk Output SPI clock signal
mosi Output Master Out Slave In
miso Input Master In Slave Out
data_out Output Received data from slave
done Output Transaction completion signal

Pin Connections

  • clk: Connect to the system clock source.
  • rst: Connect to the reset signal.
  • data_in: Connect to the data source that needs to be sent to the slave.
  • start: Connect to a control signal to initiate the SPI transaction.
  • cs: Connect to the chip select signals for the slave devices.
  • spi_clk: Connect to the SPI clock line.
  • mosi: Connect to the Master Out Slave In line.
  • miso: Connect to the Master In Slave Out line from the slave.
  • data_out: Connect to the data sink to receive data from the slave.
  • done: Connect to a control signal to indicate the end of the transaction.

Waveform Section

Below is a typical waveform for the SPI Master-Slave communication system:

Screenshot 2024-07-21 085508

Explanation

  • SPI Clock (spi_clk): The clock signal generated by the SPI master.
  • Master Out Slave In (mosi): Data line carrying bits from master to slave.
  • Master In Slave Out (miso): Data line carrying bits from slave to master.
  • Chip Select (cs): Signal to select the active slave device.
  • Data Transfer: Data is transferred on the rising edge of spi_clk.

How to Run the Project

Prerequisites

  • Verilog simulator (e.g., ModelSim, Xilinx Vivado ,Icarus Verilog)
  • FPGA development board (optional for hardware testing)

Steps

  1. Clone the Repository 
    [git clone](https://github.com/GauravDhak/SPI-Master-Slave-Communication-System/edit/main/README.md)
cd spi-master-slave