FPGATriggerer.gprj

<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
    <FileList>
        <File path="src/cmd_handler.v" type="file.verilog" enable="1"/>
        <File path="src/commands.v" type="file.verilog" enable="1"/>
        <File path="src/delay_module.v" type="file.verilog" enable="1"/>
        <File path="src/digital_edge_detector.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/>
        <File path="src/main.v" type="file.verilog" enable="1"/>
        <File path="src/pulse_extender.v" type="file.verilog" enable="1"/>
        <File path="src/target_resetter.v" type="file.verilog" enable="1"/>
        <File path="src/uart.v" type="file.verilog" enable="1"/>
        <File path="src/FPGATriggerer.cst" type="file.cst" enable="1"/>
        <File path="src/FPGATriggerer.sdc" type="file.sdc" enable="1"/>
        <File path="src/FPGATriggerer.rao" type="file.gao" enable="0"/>
    </FileList>
</Project>