From 67b129c129dcd276eb715b7a56a17df75bb2840e Mon Sep 17 00:00:00 2001
From: ThisKappaIsGrey <thanatechaumnuaiwit@gmail.com>
Date: Mon, 11 Dec 2023 18:06:23 -0800
Subject: [PATCH] Change the tests to the other format

---
 .../tests/{simple-mux.sv => simple-mux.ys}        | 11 ++++++++---
 backends/lakeroad/tests/simple-mux1.ys            | 15 +++++++++++++++
 backends/lakeroad/tests/simple-not.sv             | 14 --------------
 backends/lakeroad/tests/simple-not.ys             |  6 ++++++
 4 files changed, 29 insertions(+), 17 deletions(-)
 rename backends/lakeroad/tests/{simple-mux.sv => simple-mux.ys} (61%)
 create mode 100644 backends/lakeroad/tests/simple-mux1.ys
 delete mode 100644 backends/lakeroad/tests/simple-not.sv
 create mode 100644 backends/lakeroad/tests/simple-not.ys

diff --git a/backends/lakeroad/tests/simple-mux.sv b/backends/lakeroad/tests/simple-mux.ys
similarity index 61%
rename from backends/lakeroad/tests/simple-mux.sv
rename to backends/lakeroad/tests/simple-mux.ys
index 0dfcf0a5f4f..b10cff16a57 100644
--- a/backends/lakeroad/tests/simple-mux.sv
+++ b/backends/lakeroad/tests/simple-mux.ys
@@ -1,5 +1,4 @@
-// RUN: "$YOSYS" -p 'read_verilog -sv %s; prep -top test; pmuxtree;\
-// RUN: proc; opt; memory; opt; techmap; opt; abc; opt; write_lakeroad'
+read_verilog -sv <<EOF
 module test(input [2:0] a, output [2:0] out);
   // assign out = ~ a;
   always_comb begin
@@ -12,4 +11,10 @@ module test(input [2:0] a, output [2:0] out);
 	  endcase
   end
 endmodule
-
+EOF
+# Optimize out the mux to simple gates.
+prep -top test; pmuxtree;
+proc; opt; memory; opt;
+techmap; opt;
+abc; opt;
+write_lakeroad
diff --git a/backends/lakeroad/tests/simple-mux1.ys b/backends/lakeroad/tests/simple-mux1.ys
new file mode 100644
index 00000000000..bb6362e5a9f
--- /dev/null
+++ b/backends/lakeroad/tests/simple-mux1.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOF
+/* This module is generated by using "simple-mux.ys" + "write_verilog -noattr simple-mux.v". Delete this once you find the problem(most likely due to attributes). */
+module test(a, out);
+  wire _0_;
+  input [2:0] a;
+  wire [2:0] a;
+  output [2:0] out;
+  wire [2:0] out;
+  assign _0_ = a[0] & a[1];
+  assign out[1] = ~(a[1] | a[2]);
+  assign out[0] = a[2] | _0_;
+  assign out[2] = 1'h0;
+endmodule
+EOF
+write_lakeroad
diff --git a/backends/lakeroad/tests/simple-not.sv b/backends/lakeroad/tests/simple-not.sv
deleted file mode 100644
index f498c4466ed..00000000000
--- a/backends/lakeroad/tests/simple-not.sv
+++ /dev/null
@@ -1,14 +0,0 @@
-// RUN: "$YOSYS" -p 'read_verilog -sv %s; prep -top test; write_lakeroad' \
-// RUN:   | FileCheck %s
-module test(input a, output out);
-  assign out = ~ a;
-endmodule
-
-// CHECK: (let v0 (Wire "v0" 1))
-// CHECK: (let v1 (Wire "v1" 1))
-// CHECK: (union v1 (Op1 (Not) v0))
-// CHECK: (let a (Var "a" 1))
-// CHECK: (union v0 a)
-// CHECK: (let out v1)
-// CHECK: (delete (Wire "v0" 1))
-// CHECK: (delete (Wire "v1" 1))
diff --git a/backends/lakeroad/tests/simple-not.ys b/backends/lakeroad/tests/simple-not.ys
new file mode 100644
index 00000000000..90c2a57bb1d
--- /dev/null
+++ b/backends/lakeroad/tests/simple-not.ys
@@ -0,0 +1,6 @@
+read_verilog -sv <<EOF
+module test(input a, output out);
+  assign out = ~ a;
+endmodule
+EOF
+write_lakeroad