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divider.flow.rpt
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divider.flow.rpt
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Flow report for divider
Fri Apr 14 12:15:18 2017
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------+
; Flow Summary ;
+--------------------------------+------------------------------------------+
; Flow Status ; Successful - Fri Apr 14 12:15:18 2017 ;
; Quartus II Version ; 9.1 Build 222 10/21/2009 SJ Full Version ;
; Revision Name ; divider ;
; Top-level Entity Name ; divider ;
; Family ; Stratix II GX ;
; Device ; EP2SGX130GF1508C3 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 24 / 106,032 ( < 1 % ) ;
; Dedicated logic registers ; 8 / 106,032 ( < 1 % ) ;
; Total registers ; 8 ;
; Total pins ; 25 / 843 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 6,747,840 ( 0 % ) ;
; DSP block 9-bit elements ; 0 / 504 ( 0 % ) ;
; Total GXB Receiver Channels ; 0 / 20 ( 0 % ) ;
; Total GXB Transmitter Channels ; 0 / 20 ( 0 % ) ;
; Total PLLs ; 0 / 8 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
+--------------------------------+------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/14/2017 12:14:41 ;
; Main task ; Compilation ;
; Revision Name ; divider ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+--------------------------------------+---------------------------------+---------------+-------------+-----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+--------------------------------------+---------------------------------+---------------+-------------+-----------------+
; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 115410752129008.149214328108608 ; -- ; -- ; -- ;
; EDA_DESIGN_INSTANCE_NAME ; divider_vlg_tst ; -- ; -- ; divider_vlg_tst ;
; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; divider_vlg_tst ; -- ; -- ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_simulation ;
; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ;
; EDA_TEST_BENCH_FILE ; simulation/modelsim/divider.vt ; -- ; -- ; divider_vlg_tst ;
; EDA_TEST_BENCH_MODULE_NAME ; divider_vlg_tst ; -- ; -- ; divider_vlg_tst ;
; EDA_TEST_BENCH_NAME ; divider_vlg_tst ; -- ; -- ; eda_simulation ;
; EDA_TIME_SCALE ; 100 ns ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+--------------------------------------+---------------------------------+---------------+-------------+-----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 244 MB ; 00:00:02 ;
; Fitter ; 00:00:19 ; 1.3 ; 591 MB ; 00:00:22 ;
; Assembler ; 00:00:11 ; 1.0 ; 532 MB ; 00:00:11 ;
; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 200 MB ; 00:00:01 ;
; Total ; 00:00:33 ; -- ; -- ; 00:00:36 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; sususweet ; Windows Vista ; 6.2 ; x86_64 ;
; Fitter ; sususweet ; Windows Vista ; 6.2 ; x86_64 ;
; Assembler ; sususweet ; Windows Vista ; 6.2 ; x86_64 ;
; Classic Timing Analyzer ; sususweet ; Windows Vista ; 6.2 ; x86_64 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off divider -c divider
quartus_fit --read_settings_files=off --write_settings_files=off divider -c divider
quartus_asm --read_settings_files=off --write_settings_files=off divider -c divider
quartus_tan --read_settings_files=off --write_settings_files=off divider -c divider --timing_analysis_only