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Triggering pdbg sreset yields machine check on P9 sforza #42

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Dichloromethane opened this issue Apr 11, 2019 · 2 comments
Open

Triggering pdbg sreset yields machine check on P9 sforza #42

Dichloromethane opened this issue Apr 11, 2019 · 2 comments

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@Dichloromethane
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Dichloromethane commented Apr 11, 2019

After running the following commands from the BMC on my Talos 2 (single 8-core Sforza chip), the entire p9 chip crashed:

# pdbg -p0 -c13 -a stop
# pdbg -p0 -c13 -t0 sreset

After I restarted the computer, the following message greeted me:

13.41986|================================================
13.41987|Error reported by prdf (0xE500) PLID 0x90000002
13.41988| PRD Signature : 0x7000D 0xDD3F001A
13.42284| Signature Description : pu.core:k0:n0:s0:p00:c13 (COREFIR[26]) Core errors while in maintenance mode
13.42619| UserData1 : 0x0007000d00000101
13.42620| UserData2 : 0xdd3f001a00000000
13.42621|------------------------------------------------
13.42851| Callout type : Procedure Callout
13.42852| Procedure : EPUB_PRC_LVL_SUPP
13.42853| Priority : SRCI_PRIORITY_MED
13.42854|------------------------------------------------
13.42854|
13.42855|------------------------------------------------
13.42856| System checkstop occurred during runtime on previous boot
13.42857|------------------------------------------------
13.42857|
13.42858|------------------------------------------------
13.42858| Hostboot Build ID:
13.42859|================================================

@Dichloromethane
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I don't know whether this is a bug in pdbg or the chip, but even if it is a problem with the chip, maybe adding a safety check would be appropriate?

@apopple
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apopple commented Apr 17, 2019

Thanks for the report. Based on the above it looks like it is most probably a bug in pdbg.

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