About the fence inst in second_stage_only_translation

[cebarobot]

Hi, I find there is something strange in second_stage_only_translation:

riscv-hyp-tests/translation_tests.c

Lines 130 to 141 in 98701e3

	goto_priv(PRIV_VS);
	TEST_SETUP_EXCEPT();
	bool check1 = read64(vaddr1) == 0x11;
	bool check2 = read64(vaddr2) == 0x22;
	TEST_ASSERT("vs gets right values", excpt.triggered == false && check1 && check2);
	hpt_switch();
	sfence();
	TEST_SETUP_EXCEPT();
	check1 = read64(vaddr1) == 0x22;
	check2 = read64(vaddr2) == 0x11;
	TEST_ASSERT("vs gets right values after changing pt", excpt.triggered == false && check1 && check2);

In this section of code, the program switches the G-stage (2nd stage) page table by hpt_switch() in VS-mode, then tries to flush TLB using sfence.vma by sfence().

Accodring to the latest risc-v priv spec, sfence.vma could not affect 2nd-stage address translation. I think hfence.gvma should be used here.

Section: Hypervisor Memory-Management Fence Instructions
Instruction SFENCE.VMA applies only to the memory-management data structures controlled by the current satp (either the HS-level satp when V=0 or vsatp when V=1).

Also, Switching the G-stage table in VS-mode is really unusual. It should be done in HS-mode.

I think line 136-137 of codes should be modified like below:

 goto_priv(PRIV_HS); 
 hpt_switch(); 
 hfence_gvma(); 
 goto_priv(PRIV_VS);

I'm not sure if my analysis is correct. If correct, I could open an PR to fix this problem.

Thanks a lot.