From 4f33086fc51b7c6d9bf79cfc4593d0814f5063f1 Mon Sep 17 00:00:00 2001 From: Leifu Zhao Date: Mon, 21 Aug 2023 13:04:25 +0800 Subject: [PATCH 1/7] pm: add specific power management support for mtl Adds mtl specific sram sleep and sram power. Signed-off-by: Leifu Zhao --- bsp_sedi/soc/intel_ish/pm/aon/aon_task.c | 134 ++++++++++++++++++++++- bsp_sedi/soc/intel_ish/pm/pm_regs.h | 4 + 2 files changed, 132 insertions(+), 6 deletions(-) diff --git a/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c b/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c index fae286a..36de5d6 100644 --- a/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c +++ b/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c @@ -310,6 +310,78 @@ static int restore_main_fw(void) #define SRAM_POWER_OFF_BANKS CONFIG_RAM_BANKS +/* SRAM needs time to enter retention mode */ +#define CYCLES_PER_US 100 +#define SRAM_RETENTION_US_DELAY 5 +#define SRAM_RETENTION_CYCLES_DELAY (SRAM_RETENTION_US_DELAY * CYCLES_PER_US) + +#ifdef CONFIG_SOC_INTEL_ISH_5_6_0 +#define SRAM_WARM_UP_COUNTER (1000) +#define SRAM_CTRL_ERASE_SIZE_BIT 2 +#define SRAM_CTRL_ERASE_BYTE_TO_QWORD 3 +#define SRAM_BANK_ERASE_SIZE \ + ((CONFIG_RAM_BANK_SIZE >> SRAM_CTRL_ERASE_BYTE_TO_QWORD) \ + << SRAM_CTRL_ERASE_SIZE_BIT) +#define SRAM_TILES (CONFIG_RAM_BANKS * 2) + +static uint32_t sram_toggle_tile(uint32_t tile_id, uint32_t enable) +{ + uint32_t pmu_sram_val = read32(PMU_SRAM_PG_EN); + uint32_t pmu_toggle_bit = (1 << tile_id); + uint32_t u = 0; + + if (enable && (pmu_sram_val & pmu_toggle_bit)) { + pmu_sram_val &= ~pmu_toggle_bit; + write32(PMU_SRAM_PG_EN, pmu_sram_val); + while (!(pmu_toggle_bit & read32(PMU_SRAM_PWR_STATUS))) + ; + for (u = 0; u < SRAM_WARM_UP_COUNTER; ++u) + __asm__ volatile ("nop"); + } else if (!enable && (~pmu_sram_val & pmu_toggle_bit)) { + pmu_sram_val |= pmu_toggle_bit; + write32(PMU_SRAM_PG_EN, pmu_sram_val); + while ((pmu_toggle_bit & read32(PMU_SRAM_PWR_STATUS))) + ; + for (u = 0; u < SRAM_WARM_UP_COUNTER; ++u) + __asm__ volatile ("nop"); + } else { + enable = 0; + } + return enable; +} + +static void sram_toggle_bank(unsigned int bank_number, unsigned int enable) +{ + uint32_t tile_id = bank_number << 1; + + if (enable) { + if (sram_toggle_tile(tile_id, enable) && + sram_toggle_tile((tile_id + 1), enable)) { + write32(ISH_SRAM_CTRL_ERASE_ADDR, + CONFIG_RAM_BASE + + bank_number * CONFIG_RAM_BANK_SIZE); + write32(ISH_SRAM_CTRL_ERASE_CTRL, (SRAM_BANK_ERASE_SIZE | 0x1)); + while (read32(ISH_SRAM_CTRL_ERASE_CTRL) & 0x1) + ; + } + } else { + sram_toggle_tile(tile_id, enable); + sram_toggle_tile((tile_id + 1), enable); + } + + write32(ISH_SRAM_CTRL_INTR, read32(ISH_SRAM_CTRL_INTR)); +} + +static void sram_power(int on) +{ + int i; + + for (i = 0; i < SRAM_POWER_OFF_BANKS; i++) { + sram_toggle_bank(i, on); + } +} +#else + /** * check SRAM bank i power gated status in PMU_SRAM_PG_EN register * 1: power gated 0: not power gated @@ -342,11 +414,6 @@ static int restore_main_fw(void) /* SRAM needs time to warm up after power on */ #define SRAM_WARM_UP_DELAY_CNT 10 -/* SRAM needs time to enter retention mode */ -#define CYCLES_PER_US 100 -#define SRAM_RETENTION_US_DELAY 5 -#define SRAM_RETENTION_CYCLES_DELAY (SRAM_RETENTION_US_DELAY * CYCLES_PER_US) - static void sram_power(int on) { int i; @@ -395,6 +462,7 @@ static void sram_power(int on) } } +#endif #define RTC_TICKS_IN_SECOND 32768 @@ -498,15 +566,65 @@ static inline void clear_vnnred_aoncg(void) write32(CCU_AONCG_EN, 0); } +#ifdef CONFIG_SOC_INTEL_ISH_5_6_0 +#define STRINGIFY(x) #x +#define SLINE(num) STRINGIFY(num) +#define RETENTION_EXIT_CYCLES_DELAY 5 + +static void sram_enter_sleep_mode(void) +{ + uint32_t val, sum_mask, mask; + + sum_mask = mask = 0x1; + val = read32(PMU_SRAM_DEEPSLEEP); + while (sum_mask <= CONFIG_RAM_BANK_TILE_MASK) { + if (!(val & mask)) { + write32(PMU_SRAM_DEEPSLEEP, val | sum_mask); + while (read32(PMU_SRAM_PWR_STATUS) & mask) + ; + } + mask <<= 1; + sum_mask += mask; + } +} + +static void sram_exit_sleep_mode(void) +{ + uint32_t val, sum_mask, mask; + + sum_mask = mask = 0x1; + val = read32(PMU_SRAM_DEEPSLEEP); + while (sum_mask <= CONFIG_RAM_BANK_TILE_MASK) { + if ((val & mask)) { + write32(PMU_SRAM_DEEPSLEEP, val & ~sum_mask); + while (!(read32(PMU_SRAM_PWR_STATUS) & mask)) + ; + __asm__ volatile ( + "movl $"SLINE(RETENTION_EXIT_CYCLES_DELAY)", %%ecx;" + "loop .;\n\t" + : + : + : "ecx" + ); + } + mask <<= 1; + sum_mask += mask; + } +} +#endif + static void handle_d0i2(void) { pg_exit_save_ctx(); aon_share.pg_exit = 0; +#ifdef CONFIG_SOC_INTEL_ISH_5_6_0 + sram_enter_sleep_mode(); +#else /* set main SRAM into retention mode*/ write32(PMU_LDO_CTRL, (PMU_LDO_ENABLE_BIT | PMU_LDO_RETENTION_BIT)); - +#endif /* delay some cycles before halt */ delay(SRAM_RETENTION_CYCLES_DELAY); @@ -532,6 +650,9 @@ static void handle_d0i2(void) if (read32(PMU_RST_PREP) & PMU_RST_PREP_AVAIL) handle_reset(ISH_PM_STATE_RESET_PREP); +#ifdef CONFIG_SOC_INTEL_ISH_5_6_0 + sram_exit_sleep_mode(); +#else /* set main SRAM intto normal mode */ write32(PMU_LDO_CTRL, PMU_LDO_ENABLE_BIT); @@ -541,6 +662,7 @@ static void handle_d0i2(void) */ while (!(read32(PMU_LDO_CTRL) & PMU_LDO_READY_BIT)) continue; +#endif if (aon_share.pg_exit) ish_dma_set_msb(PAGING_CHAN, aon_share.uma_msb, diff --git a/bsp_sedi/soc/intel_ish/pm/pm_regs.h b/bsp_sedi/soc/intel_ish/pm/pm_regs.h index e51c1c2..e8cbe3f 100644 --- a/bsp_sedi/soc/intel_ish/pm/pm_regs.h +++ b/bsp_sedi/soc/intel_ish/pm/pm_regs.h @@ -15,6 +15,8 @@ /* PMU Registers */ #define PMU_SRAM_PG_EN (SEDI_PMU_BASE + 0x0) +#define PMU_SRAM_PWR_STATUS (SEDI_PMU_BASE + 0xF60) +#define PMU_SRAM_DEEPSLEEP (SEDI_PMU_BASE + 0xF38) #define PMU_PMC_HOST_RST_CTL (SEDI_PMU_BASE + 0xF20) #define PMU_SW_PG_REQ (SEDI_PMU_BASE + 0xF14) #define PMU_PMC_PG_WAKE (SEDI_PMU_BASE + 0xF18) @@ -222,6 +224,8 @@ #define CONFIG_RAM_SIZE 0x000A0000 #define CONFIG_RAM_BANK_SIZE 0x00010000 #define CONFIG_RAM_BANKS (CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE) +#define CONFIG_RAM_BANK_MASK 0xFFFFF +#define CONFIG_RAM_BANK_TILE_MASK (CONFIG_RAM_BANK_MASK) #define AON_SP_RESERVED (8) From b2711b90cee0230933ac2f62496bd069c038ab91 Mon Sep 17 00:00:00 2001 From: Leifu Zhao Date: Tue, 22 Aug 2023 14:42:50 +0800 Subject: [PATCH 2/7] pm: add api to control handling d3 interrupt Adds the api function to control how to handle d3 interrupt. Signed-off-by: Leifu Zhao --- bsp_sedi/soc/intel_ish/pm/aon/aon_share.h | 3 +++ bsp_sedi/soc/intel_ish/pm/aon/aon_task.c | 6 ++++-- bsp_sedi/soc/intel_ish/pm/ish_pm.c | 8 +++++++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/bsp_sedi/soc/intel_ish/pm/aon/aon_share.h b/bsp_sedi/soc/intel_ish/pm/aon/aon_share.h index 9048da1..d244753 100644 --- a/bsp_sedi/soc/intel_ish/pm/aon/aon_share.h +++ b/bsp_sedi/soc/intel_ish/pm/aon/aon_share.h @@ -55,6 +55,9 @@ struct ish_aon_share { */ uint32_t main_fw_rw_addr; uint32_t main_fw_rw_size; + + /* host suspend state */ + uint32_t host_in_suspend; } __attribute__((packed)); #endif /* _AON_SHARE_H_ */ diff --git a/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c b/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c index 36de5d6..fdd1985 100644 --- a/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c +++ b/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c @@ -850,8 +850,10 @@ void ish_aon_main(void) /* check if D3 rising status */ if (read32(PMU_D3_STATUS) & (PMU_D3_BIT_RISING_EDGE_STATUS | PMU_D3_BIT_SET)) { - aon_share.pm_state = ISH_PM_STATE_D3; - handle_d3(); + if (!(aon_share.host_in_suspend)) { + aon_share.pm_state = ISH_PM_STATE_D3; + handle_d3(); + } } /* restore main FW's IDT and switch back to main FW */ diff --git a/bsp_sedi/soc/intel_ish/pm/ish_pm.c b/bsp_sedi/soc/intel_ish/pm/ish_pm.c index 9955958..eef008b 100644 --- a/bsp_sedi/soc/intel_ish/pm/ish_pm.c +++ b/bsp_sedi/soc/intel_ish/pm/ish_pm.c @@ -493,7 +493,8 @@ static void handle_d3(uint32_t irq_vec) write32(SEDI_IOAPIC_EOI, irq_vec); write32(LAPIC_EOI, 0x0); - ish_pm_reset(ISH_PM_STATE_D3); + if (!(pm_ctx.aon_share->host_in_suspend)) + ish_pm_reset(ISH_PM_STATE_D3); } } @@ -583,6 +584,11 @@ void sedi_pm_reset(void) ish_mia_reset(); } +void sedi_pm_host_suspend(uint32_t suspend) +{ + pm_ctx.aon_share->host_in_suspend = suspend; +} + /* * helper for print idle_stats */ From 73492199f4ab7901a423c0740e24fc9a8bee9680 Mon Sep 17 00:00:00 2001 From: Leifu Zhao Date: Tue, 22 Aug 2023 15:01:29 +0800 Subject: [PATCH 3/7] pm: change d0i1 from TCG to MIA SS BCG for mtl Changes mtl d0i1 from using TCG to use MIA SS BCG. Signed-off-by: Leifu Zhao --- bsp_sedi/soc/intel_ish/pm/ish_pm.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/bsp_sedi/soc/intel_ish/pm/ish_pm.c b/bsp_sedi/soc/intel_ish/pm/ish_pm.c index eef008b..04cf24d 100644 --- a/bsp_sedi/soc/intel_ish/pm/ish_pm.c +++ b/bsp_sedi/soc/intel_ish/pm/ish_pm.c @@ -316,33 +316,47 @@ static void enter_d0i0(void) static void enter_d0i1(void) { +#ifndef CONFIG_SOC_INTEL_ISH_5_6_0 uint64_t ioapic_state; +#endif uint64_t t0, t1; +#ifndef CONFIG_SOC_INTEL_ISH_5_6_0 ioapic_state = sedi_core_get_irq_map(); pm_disable_irqs(ioapic_state); +#endif sedi_core_irq_enable(SEDI_IRQ_PMU2IOAPIC); sedi_core_irq_enable(SEDI_IRQ_RESET_PREP); t0 = sedi_rtc_get_us(); pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I1; +#ifndef CONFIG_SOC_INTEL_ISH_5_6_0 /* enable Trunk Clock Gating (TCG) of ISH */ write32(CCU_TCG_EN, 1); +#else + write32(CCU_BCG_MIA, read32(CCU_BCG_MIA) | CCU_BCG_BIT_MIA); +#endif /* halt ISH cpu, will wakeup from PMU wakeup interrupt */ ish_mia_halt(); +#ifndef CONFIG_SOC_INTEL_ISH_5_6_0 /* disable Trunk Clock Gating (TCG) of ISH */ write32(CCU_TCG_EN, 0); +#else + write32(CCU_BCG_MIA, read32(CCU_BCG_MIA) & (~CCU_BCG_BIT_MIA)); +#endif pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0; t1 = sedi_rtc_get_us(); log_pm_stat(&pm_stats.d0i1, t0, t1); +#ifndef CONFIG_SOC_INTEL_ISH_5_6_0 /* restore interrupts */ pm_enable_irqs(ioapic_state); - sedi_core_irq_enable(SEDI_IRQ_PMU2IOAPIC); +#endif + sedi_core_irq_disable(SEDI_IRQ_PMU2IOAPIC); } static void enter_d0i2(void) @@ -386,7 +400,7 @@ static void enter_d0i2(void) /* restore interrupts */ pm_enable_irqs(ioapic_state); - sedi_core_irq_enable(SEDI_IRQ_PMU2IOAPIC); + sedi_core_irq_disable(SEDI_IRQ_PMU2IOAPIC); } static void enter_d0i3(void) @@ -430,7 +444,7 @@ static void enter_d0i3(void) /* restore interrupts */ pm_enable_irqs(ioapic_state); - sedi_core_irq_enable(SEDI_IRQ_PMU2IOAPIC); + sedi_core_irq_disable(SEDI_IRQ_PMU2IOAPIC); } static void pre_setting_d0ix(void) @@ -448,9 +462,13 @@ void sedi_pm_enter_power_state(int state) { switch (state) { case ISH_PM_STATE_D0I1: +#ifndef CONFIG_SOC_INTEL_ISH_5_6_0 pre_setting_d0ix(); +#endif enter_d0i1(); +#ifndef CONFIG_SOC_INTEL_ISH_5_6_0 post_setting_d0ix(); +#endif break; case ISH_PM_STATE_D0I2: pre_setting_d0ix(); From ffbdcaa26e7d74583c0737d6efc5e3055a63fe05 Mon Sep 17 00:00:00 2001 From: Leifu Zhao Date: Tue, 22 Aug 2023 15:23:36 +0800 Subject: [PATCH 4/7] pm: change irq vectors for pmu, pci, reset prep Changes irq vectors for pmu, pci, reset preo to avoid conflict. Signed-off-by: Leifu Zhao --- bsp_sedi/soc/intel_ish/pm/ish_pm.c | 6 +++--- bsp_sedi/soc/intel_ish/pm/pm_regs.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/bsp_sedi/soc/intel_ish/pm/ish_pm.c b/bsp_sedi/soc/intel_ish/pm/ish_pm.c index 04cf24d..6313d90 100644 --- a/bsp_sedi/soc/intel_ish/pm/ish_pm.c +++ b/bsp_sedi/soc/intel_ish/pm/ish_pm.c @@ -568,9 +568,9 @@ void sedi_pm_init(void) write32(PMU_ISH_FABRIC_CNT, (read32(PMU_ISH_FABRIC_CNT) & 0xffff0000) | FABRIC_IDLE_COUNT); write32(PMU_PGCB_CLKGATE_CTRL, TRUNK_CLKGATE_COUNT); - IRQ_CONNECT(SEDI_IRQ_RESET_PREP, 2, reset_prep_isr, 0, IOAPIC_LEVEL); - IRQ_CONNECT(SEDI_IRQ_PMU2IOAPIC, 2, pmu_wakeup_isr, 0, IOAPIC_LEVEL); - IRQ_CONNECT(SEDI_IRQ_PCIEDEV, 2, pcie_dev_isr, 0, IOAPIC_LEVEL); + IRQ_CONNECT(SEDI_IRQ_RESET_PREP, 5, reset_prep_isr, 0, IOAPIC_LEVEL); + IRQ_CONNECT(SEDI_IRQ_PMU2IOAPIC, 5, pmu_wakeup_isr, 0, IOAPIC_LEVEL); + IRQ_CONNECT(SEDI_IRQ_PCIEDEV, 5, pcie_dev_isr, 0, IOAPIC_LEVEL); /* unmask reset prep avail interrupt */ write32(PMU_RST_PREP, 0); diff --git a/bsp_sedi/soc/intel_ish/pm/pm_regs.h b/bsp_sedi/soc/intel_ish/pm/pm_regs.h index e8cbe3f..9caf619 100644 --- a/bsp_sedi/soc/intel_ish/pm/pm_regs.h +++ b/bsp_sedi/soc/intel_ish/pm/pm_regs.h @@ -215,9 +215,9 @@ #define IOAPIC_NUM_RTES 64 -#define SEDI_VEC_RESET_PREP 64 -#define SEDI_VEC_PMU2IOAPIC 65 -#define SEDI_VEC_PCIEDEV 66 +#define SEDI_VEC_RESET_PREP 112 +#define SEDI_VEC_PMU2IOAPIC 113 +#define SEDI_VEC_PCIEDEV 114 /* SRAM memory definitions */ #define CONFIG_RAM_BASE 0xFF200000 From 8022b0310a297cf3a98218d3006fef18a7d06af6 Mon Sep 17 00:00:00 2001 From: Dong Wang Date: Tue, 5 Sep 2023 20:57:51 +0800 Subject: [PATCH 5/7] pm: correct the macro for uart register base need to change after switching to osxml register header files Signed-off-by: Dong Wang --- bsp_sedi/soc/intel_ish/pm/ish_pm.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/bsp_sedi/soc/intel_ish/pm/ish_pm.c b/bsp_sedi/soc/intel_ish/pm/ish_pm.c index 6313d90..006233c 100644 --- a/bsp_sedi/soc/intel_ish/pm/ish_pm.c +++ b/bsp_sedi/soc/intel_ish/pm/ish_pm.c @@ -40,22 +40,22 @@ static sedi_uart_config_t uart0_cfg, uart1_cfg, uart2_cfg; static void uart_to_idle(void) { sedi_uart_get_config(SEDI_UART_0, &uart0_cfg); - write32(SEDI_UART_0_BASE + LCR, 0x80); - write32(SEDI_UART_0_BASE + DLL, 0x1); - write32(SEDI_UART_0_BASE + DLH, 0x0); - write32(SEDI_UART_0_BASE + LCR, 0); + write32(SEDI_IREG_BASE(UART, 0) + LCR, 0x80); + write32(SEDI_IREG_BASE(UART, 0) + DLL, 0x1); + write32(SEDI_IREG_BASE(UART, 0) + DLH, 0x0); + write32(SEDI_IREG_BASE(UART, 0) + LCR, 0); sedi_uart_get_config(SEDI_UART_0, &uart1_cfg); - write32(SEDI_UART_1_BASE + LCR, 0x80); - write32(SEDI_UART_1_BASE + DLL, 0x1); - write32(SEDI_UART_1_BASE + DLH, 0x0); - write32(SEDI_UART_1_BASE + LCR, 0); + write32(SEDI_IREG_BASE(UART, 1) + LCR, 0x80); + write32(SEDI_IREG_BASE(UART, 1) + DLL, 0x1); + write32(SEDI_IREG_BASE(UART, 1) + DLH, 0x0); + write32(SEDI_IREG_BASE(UART, 1) + LCR, 0); sedi_uart_get_config(SEDI_UART_0, &uart2_cfg); - write32(SEDI_UART_2_BASE + LCR, 0x80); - write32(SEDI_UART_2_BASE + DLL, 0x1); - write32(SEDI_UART_2_BASE + DLH, 0x0); - write32(SEDI_UART_2_BASE + LCR, 0); + write32(SEDI_IREG_BASE(UART, 2) + LCR, 0x80); + write32(SEDI_IREG_BASE(UART, 2) + DLL, 0x1); + write32(SEDI_IREG_BASE(UART, 2) + DLH, 0x0); + write32(SEDI_IREG_BASE(UART, 2) + LCR, 0); } static void uart_port_restore(void) From 92f09ebd263c37423266f34c4923fd3941f013c6 Mon Sep 17 00:00:00 2001 From: Dong Wang Date: Tue, 5 Sep 2023 21:00:01 +0800 Subject: [PATCH 6/7] main: change main()'s return value as int To suppress build warning. Signed-off-by: Dong Wang --- zephyr/iut_test/src/main.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/zephyr/iut_test/src/main.c b/zephyr/iut_test/src/main.c index 28244f0..ebe0726 100644 --- a/zephyr/iut_test/src/main.c +++ b/zephyr/iut_test/src/main.c @@ -120,7 +120,7 @@ int iut_trigger(size_t argc, char **argv) return -EPERM; } -void main(void) +int main(void) { k_msleep(2000); @@ -147,4 +147,6 @@ void main(void) k_sem_give(&sem_trigger); }; + + return 0; } From b3b43d4e3da7ba483611bbbea7ef8af92c69df31 Mon Sep 17 00:00:00 2001 From: Leifu Zhao Date: Tue, 5 Sep 2023 15:36:58 +0800 Subject: [PATCH 7/7] pm: fix handling reset prep in incorrect place The handling of reset prep should be after sram exit sleep mode. Signed-off-by: Leifu Zhao --- bsp_sedi/soc/intel_ish/pm/aon/aon_task.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c b/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c index fdd1985..859314d 100644 --- a/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c +++ b/bsp_sedi/soc/intel_ish/pm/aon/aon_task.c @@ -647,9 +647,6 @@ static void handle_d0i2(void) clear_vnnred_aoncg(); - if (read32(PMU_RST_PREP) & PMU_RST_PREP_AVAIL) - handle_reset(ISH_PM_STATE_RESET_PREP); - #ifdef CONFIG_SOC_INTEL_ISH_5_6_0 sram_exit_sleep_mode(); #else @@ -664,6 +661,9 @@ static void handle_d0i2(void) continue; #endif + if (read32(PMU_RST_PREP) & PMU_RST_PREP_AVAIL) + handle_reset(ISH_PM_STATE_RESET_PREP); + if (aon_share.pg_exit) ish_dma_set_msb(PAGING_CHAN, aon_share.uma_msb, aon_share.uma_msb);