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Trusted Hardware & TEEs

This document aims to explore the topic of trusted hardware and more specifically TEEs (Trusted Execution Environments).

TODO: Brief description of what is meant by trusted hardware and trusted execution environment.

Many of the projects listed below are taken from Intel SGX Explained by Victor Costan and Srinivas Devadas.

Resources

Micro Architectural Cryptanalysis

Frameworks & SDKs

Applications

OpenTitan

https://opentitan.org/

Keystone

https://keystone-enclave.org/

Intel SGX

https://en.wikipedia.org/wiki/Software_Guard_Extensions

Educational Material

Tutorials, wikis, etc.

  • SGX Tutorial Series by Intel
  • SGX 101 by the Systems Software & Security Lab from Georgia Institute of Technology led by Prof. Taesoo Kim

Literature

Curated lists

Attacks

Production Uses

Signal Messaging Application

Remote Attestation

From https://software.intel.com/content/www/us/en/develop/download/intel-sgx-intel-epid-provisioning-and-attestation-services.html:

Each SGX enabled processor supports two statistically-unique values stored in fuses. These are known as the Root Provisioning Key and the Root Seal Key. The key transformation process operates on the Root Provisioning Key, seen here in Figure 5 (below). The Root Provisioning Key is randomly created and retained by Intel. It is the basis for how the processor demonstrates that it is a genuine Intel® SGX CPU at a specific TCB. This Root Provisioning Key is generated by a special purpose offline key generation facility, and is then delivered to Intel’s factory network. The Root Seal Key is created during processor manufacturing and is not retained by Intel. As shown in Figure 5 and Table 3 all keys except the Provisioning Key include the Root Seal Key in their derivations. This renders those keys unknown to Intel.

DCAP

https://software.intel.com/content/dam/develop/external/us/en/documents/s21c-icmc2019-intel-sgx-opensource-attestation.pdf

Literature

Code

Q&A (stackexchange, ...)

Higher level abstractions/framework

Occlum

Applications (theoretical and/or practical)

The IBM 4765 Secure Coprocessor

ARM TrustZone

The XOM Architecture

The Trusted Platform Module (TPM)

Intel's Trusted Execution Technology (TXT)

The Aegis Secure Processor

The Bastion Architecture

David Champagne and Ruby B Lee. Scalable architectural support for trusted software. In High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on, pages 1–12. IEEE, 2010.

Available at http://palms.princeton.edu/system/files/Bastion_Scalable+architectural+support+for+trusted+software.pdf

Slides by Dimitrios Skarlatos: http://cwfletcher.net/Content/598/lec18_bastion_dimitrioss.pdf

Sanctum

Ascend

Christopher W Fletcher, Marten van Dijk, and Srinivas Devadas. A secure processor architecture for encrypted computation on untrusted programs. In Proceedings of the Seventh ACM Workshop on Scalable Trusted Computing, pages 3–8. ACM, 2012.

https://dspace.mit.edu/bitstream/handle/1721.1/99986/Devadas_A%20secure.pdf

Uses Oblivious RAM techniques in the CPU's memory controller. See Intel SGX Explained by Victor Costan and Srinivas Devadas, section 4.10.

Phantom

Martin Maas, Eric Love, Emil Stefanov, Mohit Tiwari, Elaine Shi, Krste Asanovic, John Kubiatowicz, and Dawn Song. Phantom: Practical oblivious computation in a secure processor. In Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security, pages 311–324. ACM, 2013.

https://www.cs.umd.edu/~elaine/docs/phantom.pdf

Uses Oblivious RAM techniques in the CPU's memory controller. See Intel SGX Explained by Victor Costan and Srinivas Devadas, section 4.10.

HSM & TEEs

Hybrid models

HSMs and Hardware Wallets: #Zcon2Lite