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Sorry, what do you mean with "fixed sampling frequency"? The frequency is configurable from 3Khz~ to 100Mhz (and up to 400Mhz in V6). In any case, you can emulate the clock behavior with the burst mode, configure an edge trigger, set the post-capture to 2-4 samples (base it on your real clock), enable the burst mode and that's it, you get the same behavior as having a clock signal. Regarding protocols, in V6.0 you will have every analyzer from Sigrok and you could even write your own ones in Python. Cheers. |
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I'm quite impressed with this overall. I have used Salae Logic quite a bit in the past but what's always put me off is of course the 16 channel limitation.
What I feel is missing is the support of a clock signal. Right now I have a slow-stepping 6502 system and I only get to see 1 transition when I use the pattern trigger. Because the fixed sampling frequency is so high, I see nothing else. Will you be adding support for a clock signal in the future?
The only other thing for me is the need for a protocol analyser that would show an 16-bit address and 8-bit data bus as hex. I get the feeling I could write a custom one (I am more a software dev than an electronics guru anyway) but I wouldn't go down that path without the support of a clock signal.
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