diff --git a/example/HTG9200/fpga_10g/README.md b/example/HTG9200/fpga_25g/README.md similarity index 100% rename from example/HTG9200/fpga_10g/README.md rename to example/HTG9200/fpga_25g/README.md diff --git a/example/HTG9200/fpga_10g/common/vivado.mk b/example/HTG9200/fpga_25g/common/vivado.mk similarity index 100% rename from example/HTG9200/fpga_10g/common/vivado.mk rename to example/HTG9200/fpga_25g/common/vivado.mk diff --git a/example/HTG9200/fpga_10g/fpga.xdc b/example/HTG9200/fpga_25g/fpga.xdc similarity index 100% rename from example/HTG9200/fpga_10g/fpga.xdc rename to example/HTG9200/fpga_25g/fpga.xdc diff --git a/example/HTG9200/fpga_10g/fpga/Makefile b/example/HTG9200/fpga_25g/fpga/Makefile similarity index 99% rename from example/HTG9200/fpga_10g/fpga/Makefile rename to example/HTG9200/fpga_25g/fpga/Makefile index b0940833..3ddbe77c 100644 --- a/example/HTG9200/fpga_10g/fpga/Makefile +++ b/example/HTG9200/fpga_25g/fpga/Makefile @@ -60,6 +60,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/example/HTG9200/fpga_25g/fpga/config.tcl b/example/HTG9200/fpga_25g/fpga/config.tcl new file mode 100644 index 00000000..756e2b3a --- /dev/null +++ b/example/HTG9200/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/example/HTG9200/fpga_25g/fpga_10g/Makefile b/example/HTG9200/fpga_25g/fpga_10g/Makefile new file mode 100644 index 00000000..3ddbe77c --- /dev/null +++ b/example/HTG9200/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,115 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/i2c_master.v +SYN_FILES += rtl/si5341_i2c_init.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/example/HTG9200/fpga_25g/fpga_10g/config.tcl b/example/HTG9200/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 00000000..90aa4cae --- /dev/null +++ b/example/HTG9200/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/example/HTG9200/fpga_10g/ip/eth_xcvr_gt.tcl b/example/HTG9200/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from example/HTG9200/fpga_10g/ip/eth_xcvr_gt.tcl rename to example/HTG9200/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/example/HTG9200/fpga_10g/lib/eth b/example/HTG9200/fpga_25g/lib/eth similarity index 100% rename from example/HTG9200/fpga_10g/lib/eth rename to example/HTG9200/fpga_25g/lib/eth diff --git a/example/HTG9200/fpga_10g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt b/example/HTG9200/fpga_25g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt similarity index 100% rename from example/HTG9200/fpga_10g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt rename to example/HTG9200/fpga_25g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt diff --git a/example/HTG9200/fpga_10g/rtl/debounce_switch.v b/example/HTG9200/fpga_25g/rtl/debounce_switch.v similarity index 100% rename from example/HTG9200/fpga_10g/rtl/debounce_switch.v rename to example/HTG9200/fpga_25g/rtl/debounce_switch.v diff --git a/example/HTG9200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from example/HTG9200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/example/HTG9200/fpga_10g/rtl/fpga.v b/example/HTG9200/fpga_25g/rtl/fpga.v similarity index 100% rename from example/HTG9200/fpga_10g/rtl/fpga.v rename to example/HTG9200/fpga_25g/rtl/fpga.v diff --git a/example/HTG9200/fpga_10g/rtl/fpga_core.v b/example/HTG9200/fpga_25g/rtl/fpga_core.v similarity index 100% rename from example/HTG9200/fpga_10g/rtl/fpga_core.v rename to example/HTG9200/fpga_25g/rtl/fpga_core.v diff --git a/example/HTG9200/fpga_10g/rtl/i2c_master.v b/example/HTG9200/fpga_25g/rtl/i2c_master.v similarity index 100% rename from example/HTG9200/fpga_10g/rtl/i2c_master.v rename to example/HTG9200/fpga_25g/rtl/i2c_master.v diff --git a/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py b/example/HTG9200/fpga_25g/rtl/si5341_i2c_init.py similarity index 100% rename from example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py rename to example/HTG9200/fpga_25g/rtl/si5341_i2c_init.py diff --git a/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v b/example/HTG9200/fpga_25g/rtl/si5341_i2c_init.v similarity index 100% rename from example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v rename to example/HTG9200/fpga_25g/rtl/si5341_i2c_init.v diff --git a/example/HTG9200/fpga_10g/rtl/sync_signal.v b/example/HTG9200/fpga_25g/rtl/sync_signal.v similarity index 100% rename from example/HTG9200/fpga_10g/rtl/sync_signal.v rename to example/HTG9200/fpga_25g/rtl/sync_signal.v diff --git a/example/HTG9200/fpga_10g/tb/fpga_core/Makefile b/example/HTG9200/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from example/HTG9200/fpga_10g/tb/fpga_core/Makefile rename to example/HTG9200/fpga_25g/tb/fpga_core/Makefile diff --git a/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/HTG9200/fpga_25g/tb/fpga_core/test_fpga_core.py similarity index 100% rename from example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py rename to example/HTG9200/fpga_25g/tb/fpga_core/test_fpga_core.py