Are FINN DMA the same as vivado AXI_DMA ?

[kalahel]

Hi

I'm currently trying to write custom C driver code for a FINN project but I struggle a bit to interact and understand DMA generated by FINN.

Do they they wrap classic Vivado DMA or are they entirely custom ? Are they using the same control registers ?

Best regards,
Mat

[auphelia]

Hi @kalahel,
Another user opened a PR with this a while ago: Xilinx/finn#989
Maybe that could be helpful, they're using xrt for the C++ driver.

[fpjentzsch]

Hi,

the DMA is a custom HLS implementation here, which is instantiated here with interface directives applied here. The FINN-generated driver interacts with the resulting control registers here.

You could also use a normal Vivado DMA with your custom driver if you wish.

[kalahel]

Hi,

Thank you both for your very precise anwsers !

[kalahel]

Hi,

I previously ran this end to end finn notebook, everything went fine, now I got a vivado project and the pynq driver generated.

I modified the vivado project and tried using classic (micro) DMA IP to interact with the neural network IP.
To accommodate for the input/output size of the model I used AXI 4 Stream data width converter IP as such :

(So 32 bits from the DMA -> 392 from the data width converter -> 8 bits from the neural network IP -> 32 bits from the converter to the DMA)

The model does not have a tlast port so I connected its tvalid port to the tlast input of the converter, is this a mistake ?

When I send the 784 data (28*28 sample data from MNIST ), I have nothing in output of the model.

The code I use to control the DMA is inspired from lauri võsandi guide.

Do you have a idea of what can cause the issue ?

[kalahel]

Thanks for your reply !

I tried adding InsertTLastMarker but I struggle to find where to exactly.

I tried adding it here but I get this resulting graph :

But that does not really seems to make sense.

[fpjentzsch]

Looks alright to me. The TLastMarker_hls node will not modify your data, but simply count the number of transactions and assert tlast on the output stream once a frame is complete. In your case this will be for every transaction since your output shape is (1,1).

Although... I have not used this feature in a while and I'm not sure which settings for InsertTLastMarker(both=False, external=True, dynamic=True) would be correct for use with the default Vivado AXI DMA. I assume
both=False (only insert tlast for the output)
external=True (?)
dynamic=False (since you don't want to set the frame size via AXI-lite everytime you initialize the accelerator)
but maybe @auphelia can chime in.

[kalahel]

by inserting as my previous message, I get an error :

AssertionError: Insert tlast marker should be done
                        after inserting the FIFOs

So I tried inserting it later after the FIFO creation and before this line, but I got this error :

  File "/mnt/c/Dev/finn/src/finn/transformation/fpgadataflow/insert_tlastmarker.py", line 60, in apply
    num_iters = int(custom_op.get_number_output_values())
AttributeError: 'StreamingDataflowPartition' object has no attribute 'get_number_output_values'

Finally I even tried inserting it in make_zynq_proj.py after this line and got the same error :

  File "/mnt/c/Dev/finn/src/finn/transformation/fpgadataflow/insert_tlastmarker.py", line 60, in apply
    num_iters = int(custom_op.get_number_output_values())
AttributeError: 'StreamingDataflowPartition' object has no attribute 'get_number_output_values'

I am a bit lost on where exactly should I add this transformation.

[fpjentzsch]

What if you insert it after this line under the condition that it only applies to the middle StreamingDataflowPartition (the accelerator) and not the IDMA and ODMA partition?

If you want to use other DMAs, you shouldn't need the ZynqBuild transformation but stop at CreateStitchedIP. In general, I would recommend to use FINN's builder flow because it is more structured than the old end2end examples that call all transformations individually.

[kalahel]

Inserting it after this line with this code :

kernel_model = kernel_model.transform(InsertFIFO())
# User code start here
if ("dma" not in prefix) and ("StreamingDataflowPartition_1" in prefix):
  InsertTLastMarker(dynamic=False)
  print(f"Inserting tlast marker into {prefix}")
  # User code end here
kernel_model = kernel_model.transform(SpecializeLayers(self.fpga_part))

Did not add a tlast port :

And produced those warnings :

/mnt/c/Dev/finn/src/finn/transformation/fpgadataflow/create_stitched_ip.py:290: UserWarning: First node is not StreamingFIFO or IODMA.
                You may experience incorrect stitched-IP rtlsim or hardware
                behavior. It is strongly recommended to insert FIFOs prior to
                calling CreateStitchedIP.
                

Starting from the builder flow tutorial I don't know what should I modify/add to add a tlast port to the stitched IP since I don't find any reference to it in the DataflowBuildConfig class.