From 9ee015fc308a8b0f28ce9686ff6f606e73789d40 Mon Sep 17 00:00:00 2001 From: umarcor Date: Thu, 21 Oct 2021 18:38:16 +0200 Subject: [PATCH 1/7] ui: remove vunit.verilog (#559) --- examples/verilog/uart/run.py | 4 ++- examples/verilog/user_guide/run.py | 4 ++- examples/verilog/verilog_ams/run.py | 4 ++- tests/acceptance/artificial/verilog/run.py | 10 ++++--- vunit/ui/__init__.py | 4 +-- vunit/verilog.py | 31 ---------------------- 6 files changed, 18 insertions(+), 39 deletions(-) delete mode 100644 vunit/verilog.py diff --git a/examples/verilog/uart/run.py b/examples/verilog/uart/run.py index 96e292f7d..03b731e3e 100644 --- a/examples/verilog/uart/run.py +++ b/examples/verilog/uart/run.py @@ -15,11 +15,13 @@ """ from pathlib import Path -from vunit.verilog import VUnit +from vunit import VUnit SRC_PATH = Path(__file__).parent / "src" VU = VUnit.from_argv() +VU.add_verilog_builtins() + VU.add_library("uart_lib").add_source_files(SRC_PATH / "*.sv") VU.add_library("tb_uart_lib").add_source_files(SRC_PATH / "test" / "*.sv") diff --git a/examples/verilog/user_guide/run.py b/examples/verilog/user_guide/run.py index 956bab08b..7dc2dfa48 100644 --- a/examples/verilog/user_guide/run.py +++ b/examples/verilog/user_guide/run.py @@ -15,11 +15,13 @@ """ from pathlib import Path -from vunit.verilog import VUnit +from vunit import VUnit ROOT = Path(__file__).parent VU = VUnit.from_argv() +VU.add_verilog_builtins() + VU.add_library("lib").add_source_files(ROOT / "*.sv") VU.main() diff --git a/examples/verilog/verilog_ams/run.py b/examples/verilog/verilog_ams/run.py index b4c47912e..01fc32b18 100644 --- a/examples/verilog/verilog_ams/run.py +++ b/examples/verilog/verilog_ams/run.py @@ -7,11 +7,13 @@ # Copyright (c) 2014-2023, Lars Asplund lars.anders.asplund@gmail.com from pathlib import Path -from vunit.verilog import VUnit +from vunit import VUnit ROOT = Path(__file__).parent VU = VUnit.from_argv() +VU.add_verilog_builtins() + LIB = VU.add_library("lib") LIB.add_source_files(ROOT / "*.sv") LIB.add_source_files(ROOT / "*.vams").set_compile_option("modelsim.vlog_flags", ["-ams"]) diff --git a/tests/acceptance/artificial/verilog/run.py b/tests/acceptance/artificial/verilog/run.py index 028bc8a3a..656fa14a2 100644 --- a/tests/acceptance/artificial/verilog/run.py +++ b/tests/acceptance/artificial/verilog/run.py @@ -6,15 +6,18 @@ from pathlib import Path from glob import glob -from vunit.verilog import VUnit +from vunit import VUnit + root = Path(__file__).parent vu = VUnit.from_argv() +vu.add_verilog_builtins() + lib = vu.add_library("lib") lib2 = vu.add_library("lib2") -files = glob(str(root / "*.sv")) -for file in files: + +for file in glob(str(root / "*.sv")): if "tb_with_parameter_config" in file: lib2.add_source_files(file, defines={"DEFINE_FROM_RUN_PY": ""}) else: @@ -65,4 +68,5 @@ def post_check(output_path): configure_tb_with_parameter_config() configure_tb_same_sim_all_pass(vu) lib.module("tb_other_file_tests").scan_tests_from_file(str(root / "other_file_tests.sv")) + vu.main() diff --git a/vunit/ui/__init__.py b/vunit/ui/__init__.py index 6eddb5071..cfdf7fc93 100644 --- a/vunit/ui/__init__.py +++ b/vunit/ui/__init__.py @@ -993,8 +993,8 @@ def add_verilog_builtins(self): Add VUnit Verilog builtin libraries. .. IMPORTANT:: - Class ``vunit.verilog`` is deprecated and it will be removed in an upcoming release. - Verilog users will need to call this method explicitly in order to preserve the functionality. + As of VUnit v5, class ``vunit.verilog`` is removed. + Verilog users need to call this method explicitly in order to preserve the functionality. See :vunit_issue:`777`. """ self._builtins.add_verilog_builtins() diff --git a/vunit/verilog.py b/vunit/verilog.py deleted file mode 100644 index 4f45e60b1..000000000 --- a/vunit/verilog.py +++ /dev/null @@ -1,31 +0,0 @@ -# This Source Code Form is subject to the terms of the Mozilla Public -# License, v. 2.0. If a copy of the MPL was not distributed with this file, -# You can obtain one at http://mozilla.org/MPL/2.0/. -# -# Copyright (c) 2014-2023, Lars Asplund lars.anders.asplund@gmail.com - -""" -The main public Python interface of VUnit-Verilog. -""" - -from warnings import warn -from vunit.ui import VUnit as VUnitVHDL - - -class VUnit(VUnitVHDL): - """ - VUnit Verilog interface - """ - - # This is a temporary workaround to avoid breaking the scripts of current verilog users - def add_vhdl_builtins(self): # pylint: disable=arguments-differ - """ - Add vunit Verilog builtin libraries - """ - self._builtins.add_verilog_builtins() - builtins_deprecation_note = ( - "class 'verilog' is deprecated and it will be removed in future releases; " - "preserve the functionality using the default vunit class, along with " - "'compile_builtins=False' and 'VU.add_verilog_builtins'" - ) - warn(builtins_deprecation_note, Warning) From c2c66d4bcb020a1931806d74eef4645de2b781a9 Mon Sep 17 00:00:00 2001 From: umarcor Date: Thu, 21 Oct 2021 18:56:32 +0200 Subject: [PATCH 2/7] ui: remove 'compile_builtins'; preserve previous behaviour using 'add_vhdl_builtins' (#559) --- docs/check/user_guide.rst | 1 + docs/com/user_guide.rst | 1 + docs/logging/user_guide.rst | 1 + docs/user_guide.rst | 6 +++ examples/vhdl/array/run.py | 1 + examples/vhdl/array_axis_vcs/run.py | 1 + examples/vhdl/axi_dma/run.py | 1 + examples/vhdl/check/run.py | 1 + examples/vhdl/com/run.py | 1 + examples/vhdl/composite_generics/run.py | 1 + examples/vhdl/coverage/run.py | 1 + examples/vhdl/generate_tests/run.py | 2 + examples/vhdl/json4vhdl/run.py | 1 + examples/vhdl/logging/run.py | 2 + examples/vhdl/run/run.py | 1 + examples/vhdl/third_party_integration/run.py | 3 ++ examples/vhdl/uart/run.py | 1 + examples/vhdl/user_guide/run.py | 3 ++ examples/vhdl/user_guide/vhdl1993/run.py | 3 ++ examples/vhdl/vivado/run.py | 1 + tests/acceptance/artificial/vhdl/run.py | 6 ++- tests/acceptance/test_dependencies.py | 1 + tests/unit/test_ui.py | 1 - vunit/ui/__init__.py | 39 ++++++-------------- vunit/vhdl/check/run.py | 1 + vunit/vhdl/com/run.py | 2 + vunit/vhdl/data_types/run.py | 2 + vunit/vhdl/dictionary/run.py | 2 + vunit/vhdl/logging/run.py | 1 + vunit/vhdl/path/run.py | 2 + vunit/vhdl/random/run.py | 2 + vunit/vhdl/run/run.py | 2 + vunit/vhdl/string_ops/run.py | 2 + vunit/vhdl/verification_components/run.py | 2 + 34 files changed, 67 insertions(+), 31 deletions(-) diff --git a/docs/check/user_guide.rst b/docs/check/user_guide.rst index bb49e033b..6bcac19e8 100644 --- a/docs/check/user_guide.rst +++ b/docs/check/user_guide.rst @@ -712,6 +712,7 @@ of this check comes when you enable the check preprocessor in your VUnit run scr .. code-block:: python ui = VUnit.from_argv() + ui.add_vhdl_builtins() ui.enable_check_preprocessing() The check preprocessor scans your code for calls to ``check_relation`` and then parses ``expr`` as a VHDL relation. From diff --git a/docs/com/user_guide.rst b/docs/com/user_guide.rst index 590b52e8a..cf18b7fd2 100644 --- a/docs/com/user_guide.rst +++ b/docs/com/user_guide.rst @@ -35,6 +35,7 @@ is provided as an optional add-on to VUnit. It is compiled to the .. code-block:: python prj = VUnit.from_argv() + prj.add_vhdl_builtins() prj.add_com() The VHDL functionality is provided to your testbench with the diff --git a/docs/logging/user_guide.rst b/docs/logging/user_guide.rst index f50ba8030..62794d3f9 100644 --- a/docs/logging/user_guide.rst +++ b/docs/logging/user_guide.rst @@ -303,6 +303,7 @@ the ``run.py`` file like this: .. code-block:: python ui = VUnit.from_argv() + ui.add_vhdl_builtins() ui.enable_location_preprocessing() Regardless of method the location information is appended to the end of the log entry: diff --git a/docs/user_guide.rst b/docs/user_guide.rst index ffbc30884..3583b5224 100644 --- a/docs/user_guide.rst +++ b/docs/user_guide.rst @@ -43,6 +43,12 @@ bench or test for many different combinations of generic values. # Create VUnit instance by parsing command line arguments vu = VUnit.from_argv() + # Optionally add VUnit's builtin HDL utilities for checking, logging, communication... + # See http://vunit.github.io/hdl_libraries.html. + vu.add_vhdl_builtins() + # or + # vu.add_verilog_builtins() + # Create library 'lib' lib = vu.add_library("lib") diff --git a/examples/vhdl/array/run.py b/examples/vhdl/array/run.py index 5e292a6a8..319db4c7b 100644 --- a/examples/vhdl/array/run.py +++ b/examples/vhdl/array/run.py @@ -19,6 +19,7 @@ from vunit import VUnit VU = VUnit.from_argv() +VU.add_vhdl_builtins() VU.add_osvvm() SRC_PATH = Path(__file__).parent / "src" diff --git a/examples/vhdl/array_axis_vcs/run.py b/examples/vhdl/array_axis_vcs/run.py index 272542beb..19c7cb1e3 100644 --- a/examples/vhdl/array_axis_vcs/run.py +++ b/examples/vhdl/array_axis_vcs/run.py @@ -22,6 +22,7 @@ from vunit import VUnit VU = VUnit.from_argv() +VU.add_vhdl_builtins() VU.add_verification_components() SRC_PATH = Path(__file__).parent / "src" diff --git a/examples/vhdl/axi_dma/run.py b/examples/vhdl/axi_dma/run.py index 59235216b..eb0b60bb3 100644 --- a/examples/vhdl/axi_dma/run.py +++ b/examples/vhdl/axi_dma/run.py @@ -21,6 +21,7 @@ from vunit import VUnit VU = VUnit.from_argv() +VU.add_vhdl_builtins() VU.add_osvvm() VU.add_verification_components() diff --git a/examples/vhdl/check/run.py b/examples/vhdl/check/run.py index e87fd69b5..dbd9b72db 100644 --- a/examples/vhdl/check/run.py +++ b/examples/vhdl/check/run.py @@ -17,6 +17,7 @@ from vunit import VUnit VU = VUnit.from_argv() +VU.add_vhdl_builtins() # Enable location preprocessing but exclude all but check_false to make the example less bloated VU.enable_location_preprocessing( diff --git a/examples/vhdl/com/run.py b/examples/vhdl/com/run.py index 628296efc..f51e509f3 100644 --- a/examples/vhdl/com/run.py +++ b/examples/vhdl/com/run.py @@ -19,6 +19,7 @@ from vunit import VUnit VU = VUnit.from_argv() +VU.add_vhdl_builtins() VU.add_com() VU.add_verification_components() VU.add_osvvm() diff --git a/examples/vhdl/composite_generics/run.py b/examples/vhdl/composite_generics/run.py index 08412b6a6..ede539615 100644 --- a/examples/vhdl/composite_generics/run.py +++ b/examples/vhdl/composite_generics/run.py @@ -22,6 +22,7 @@ def encode(tb_cfg): VU = VUnit.from_argv() +VU.add_vhdl_builtins() TB_LIB = VU.add_library("tb_lib") TB_LIB.add_source_files(Path(__file__).parent / "test" / "*.vhd") diff --git a/examples/vhdl/coverage/run.py b/examples/vhdl/coverage/run.py index cc86118eb..91766ad23 100644 --- a/examples/vhdl/coverage/run.py +++ b/examples/vhdl/coverage/run.py @@ -18,6 +18,7 @@ def post_run(results): VU = VUnit.from_argv() +VU.add_vhdl_builtins() LIB = VU.add_library("lib") LIB.add_source_files(Path(__file__).parent / "*.vhd") diff --git a/examples/vhdl/generate_tests/run.py b/examples/vhdl/generate_tests/run.py index 81f40e6f2..6a0ff01a2 100644 --- a/examples/vhdl/generate_tests/run.py +++ b/examples/vhdl/generate_tests/run.py @@ -63,6 +63,8 @@ def generate_tests(obj, signs, data_widths): VU = VUnit.from_argv() +VU.add_vhdl_builtins() + LIB = VU.add_library("lib") LIB.add_source_files(Path(__file__).parent / "test" / "*.vhd") diff --git a/examples/vhdl/json4vhdl/run.py b/examples/vhdl/json4vhdl/run.py index 4904f25d4..30c2a2af1 100644 --- a/examples/vhdl/json4vhdl/run.py +++ b/examples/vhdl/json4vhdl/run.py @@ -22,6 +22,7 @@ TEST_PATH = Path(__file__).parent / "src" / "test" VU = VUnit.from_argv() +VU.add_vhdl_builtins() VU.add_json4vhdl() LIB = VU.add_library("test") diff --git a/examples/vhdl/logging/run.py b/examples/vhdl/logging/run.py index b080dec3b..e77038a22 100644 --- a/examples/vhdl/logging/run.py +++ b/examples/vhdl/logging/run.py @@ -17,6 +17,8 @@ from vunit import VUnit VU = VUnit.from_argv() +VU.add_vhdl_builtins() + VU.add_library("lib").add_source_files(Path(__file__).parent / "*.vhd") VU.main() diff --git a/examples/vhdl/run/run.py b/examples/vhdl/run/run.py index dda5c239f..b2d2fe811 100644 --- a/examples/vhdl/run/run.py +++ b/examples/vhdl/run/run.py @@ -19,6 +19,7 @@ ROOT = Path(__file__).parent VU = VUnit.from_argv() +VU.add_vhdl_builtins() LIB = VU.add_library("lib") LIB.add_source_files(ROOT / "*.vhd") diff --git a/examples/vhdl/third_party_integration/run.py b/examples/vhdl/third_party_integration/run.py index 26c7b39d8..819387d36 100644 --- a/examples/vhdl/third_party_integration/run.py +++ b/examples/vhdl/third_party_integration/run.py @@ -10,5 +10,8 @@ from vunit import VUnit VU = VUnit.from_argv() +VU.add_vhdl_builtins() + VU.add_library("lib").add_source_files(Path(__file__).parent / "test" / "*.vhd") + VU.main() diff --git a/examples/vhdl/uart/run.py b/examples/vhdl/uart/run.py index d358c2324..ee0b80cdf 100644 --- a/examples/vhdl/uart/run.py +++ b/examples/vhdl/uart/run.py @@ -18,6 +18,7 @@ from vunit import VUnit VU = VUnit.from_argv() +VU.add_vhdl_builtins() VU.add_osvvm() VU.add_verification_components() diff --git a/examples/vhdl/user_guide/run.py b/examples/vhdl/user_guide/run.py index 4a12fd430..54e4b9301 100644 --- a/examples/vhdl/user_guide/run.py +++ b/examples/vhdl/user_guide/run.py @@ -18,5 +18,8 @@ from vunit import VUnit VU = VUnit.from_argv() +VU.add_vhdl_builtins() + VU.add_library("lib").add_source_files(Path(__file__).parent / "*.vhd") + VU.main() diff --git a/examples/vhdl/user_guide/vhdl1993/run.py b/examples/vhdl/user_guide/vhdl1993/run.py index cd47de2c7..48a273f57 100644 --- a/examples/vhdl/user_guide/vhdl1993/run.py +++ b/examples/vhdl/user_guide/vhdl1993/run.py @@ -18,5 +18,8 @@ from vunit import VUnit VU = VUnit.from_argv(vhdl_standard="93") +VU.add_vhdl_builtins() + VU.add_library("lib").add_source_files(Path(__file__).parent / "*.vhd") + VU.main() diff --git a/examples/vhdl/vivado/run.py b/examples/vhdl/vivado/run.py index 3824667c5..36569470c 100644 --- a/examples/vhdl/vivado/run.py +++ b/examples/vhdl/vivado/run.py @@ -20,6 +20,7 @@ SRC_PATH = ROOT / "src" VU = VUnit.from_argv() +VU.add_vhdl_builtins() VU.add_library("lib").add_source_files(SRC_PATH / "*.vhd") VU.add_library("tb_lib").add_source_files(SRC_PATH / "test" / "*.vhd") diff --git a/tests/acceptance/artificial/vhdl/run.py b/tests/acceptance/artificial/vhdl/run.py index 42a9a29ea..0a9e155bb 100644 --- a/tests/acceptance/artificial/vhdl/run.py +++ b/tests/acceptance/artificial/vhdl/run.py @@ -11,10 +11,12 @@ root = Path(__file__).parent vu = VUnit.from_argv() +vu.add_vhdl_builtins() + lib = vu.add_library("lib") lib2 = vu.add_library("lib2") -files = glob(str(root / "*.vhd")) -for file in files: + +for file in glob(str(root / "*.vhd")): if "tb_set_generic" in file: lib2.add_source_files(file) else: diff --git a/tests/acceptance/test_dependencies.py b/tests/acceptance/test_dependencies.py index d22668454..d228f3d27 100644 --- a/tests/acceptance/test_dependencies.py +++ b/tests/acceptance/test_dependencies.py @@ -49,6 +49,7 @@ def run(value): argv.append("--clean") ui = VUnit.from_argv(argv=argv) + ui.add_vhdl_builtins() lib = ui.add_library("lib") lib.add_source_files(tb_pkg_file_name) lib.add_source_files(pkg_file_name) diff --git a/tests/unit/test_ui.py b/tests/unit/test_ui.py index 011810b3a..d36523517 100644 --- a/tests/unit/test_ui.py +++ b/tests/unit/test_ui.py @@ -1281,7 +1281,6 @@ def _create_ui_real_sim(self, *args): """Create an instance of the VUnit public interface class""" return VUnit.from_argv( argv=["--output-path=%s" % self._output_path, "--clean"] + list(args), - compile_builtins=False, ) def _run_main(self, ui, code=0, post_run=None): diff --git a/vunit/ui/__init__.py b/vunit/ui/__init__.py index cfdf7fc93..b930b5270 100644 --- a/vunit/ui/__init__.py +++ b/vunit/ui/__init__.py @@ -59,14 +59,12 @@ class VUnit(object): # pylint: disable=too-many-instance-attributes, too-many-p def from_argv( cls, argv=None, - compile_builtins: Optional[bool] = True, vhdl_standard: Optional[str] = None, ): """ Create VUnit instance from command line arguments. :param argv: Use explicit argv instead of actual command line argument - :param compile_builtins: Do not compile builtins. Used for VUnit internal testing. :param vhdl_standard: The VHDL standard used to compile files, if None the VUNIT_VHDL_STANDARD environment variable is used :returns: A :class:`.VUnit` object instance @@ -77,28 +75,21 @@ def from_argv( from vunit import VUnit prj = VUnit.from_argv() + prj.add_vhdl_builtins() .. IMPORTANT:: - Option ``compile_builtins`` is deprecated and it will be removed in an upcoming release. - VHDL users will need to call method :meth:`add_vhdl_builtins` explicitly in order to preserve the + As of VUnit v5, option ``compile_builtins`` is removed. + VHDL users need to call method :meth:`add_vhdl_builtins` explicitly in order to preserve the functionality. See :vunit_issue:`777`. - It is therefore recommended to now use the following procedure: - - .. code-block:: python - - from vunit import VUnit - prj = VUnit.from_argv(compile_builtins=False) - prj.add_vhdl_builtins() """ args = VUnitCLI().parse_args(argv=argv) - return cls.from_args(args, compile_builtins=compile_builtins, vhdl_standard=vhdl_standard) + return cls.from_args(args, vhdl_standard=vhdl_standard) @classmethod def from_args( cls, args, - compile_builtins: Optional[bool] = True, vhdl_standard: Optional[str] = None, ): """ @@ -108,23 +99,21 @@ def from_args( adding custom command line options. :param args: The parsed argument namespace object - :param compile_builtins: Do not compile builtins. Used for VUnit internal testing. :param vhdl_standard: The VHDL standard used to compile files, if None the VUNIT_VHDL_STANDARD environment variable is used :returns: A :class:`.VUnit` object instance .. IMPORTANT:: - Option ``compile_builtins`` is deprecated and it will be removed in an upcoming release. - VHDL users will need to call method :meth:`add_vhdl_builtins` explicitly in order to preserve the + As of VUnit v5, option ``compile_builtins`` is removed. + VHDL users need to call method :meth:`add_vhdl_builtins` explicitly in order to preserve the functionality. See :vunit_issue:`777`. """ - return cls(args, compile_builtins=compile_builtins, vhdl_standard=vhdl_standard) + return cls(args, vhdl_standard=vhdl_standard) def __init__( self, args, - compile_builtins: Optional[bool] = True, vhdl_standard: Optional[str] = None, ): self._args = args @@ -177,13 +166,8 @@ def test_filter(name, attribute_names): hline = "=" * 75 print(hline) LOGGER.warning( - """Option 'compile_builtins' of methods 'from_args' and 'from_argv' is deprecated. -In future releases, it will be removed and builtins will need to be added explicitly. -To prepare for upcoming changes, it is recommended to apply the following modifications in the run script now: - -* Use `from_argv(compile_builtins=False)` or `from_args(compile_builtins=False)`. -* Add an explicit call to 'add_vhdl_builtins'. - + """As of VUnit v5, option ``compile_builtins`` of methods 'from_args' and 'from_argv' is removed. +HDL builtins need to be added explicitly. See https://github.com/VUnit/vunit/issues/777. """ ) @@ -1015,9 +999,8 @@ def add_vhdl_builtins(self, external=None): ) .. IMPORTANT:: - Option ``compile_builtins`` of methods :meth:`from_argv` and :meth:`from_args` is deprecated and it will be - removed in an upcoming release. - VHDL users will need to call this method explicitly in order to preserve the functionality. + As of VUnit v5, option ``compile_builtins`` of methods :meth:`from_argv` and :meth:`from_args` is removed. + VHDL users need to call this method explicitly in order to preserve the functionality. See :vunit_issue:`777`. """ self._builtins.add_vhdl_builtins(external=external) diff --git a/vunit/vhdl/check/run.py b/vunit/vhdl/check/run.py index 55e73978c..6e75fe4d6 100644 --- a/vunit/vhdl/check/run.py +++ b/vunit/vhdl/check/run.py @@ -16,6 +16,7 @@ generate_check_match.main() VU = VUnit.from_argv() +VU.add_vhdl_builtins() LIB = VU.add_library("lib") LIB.add_source_files(Path(ROOT) / "vunit" / "vhdl" / "check" / "test" / "test_support.vhd") diff --git a/vunit/vhdl/com/run.py b/vunit/vhdl/com/run.py index 6eea2a381..c7a81d54f 100644 --- a/vunit/vhdl/com/run.py +++ b/vunit/vhdl/com/run.py @@ -10,7 +10,9 @@ ROOT = Path(__file__).parent UI = VUnit.from_argv() +UI.add_vhdl_builtins() UI.add_com() + TB_COM_LIB = UI.add_library("tb_com_lib") TB_COM_LIB.add_source_files(ROOT / "test" / "*.vhd") TB_COM_LIB.package("custom_types_pkg").generate_codecs( diff --git a/vunit/vhdl/data_types/run.py b/vunit/vhdl/data_types/run.py index e87df0ad7..78af4deb2 100644 --- a/vunit/vhdl/data_types/run.py +++ b/vunit/vhdl/data_types/run.py @@ -11,6 +11,8 @@ ROOT = Path(__file__).parent VU = VUnit.from_argv() +VU.add_vhdl_builtins() + LIB = VU.library("vunit_lib") LIB.add_source_files(ROOT / ".." / "logging" / "test" / "test_support_pkg.vhd") for fname in glob(str(ROOT / "test" / "*.vhd")): diff --git a/vunit/vhdl/dictionary/run.py b/vunit/vhdl/dictionary/run.py index 3472bf097..650acd46c 100644 --- a/vunit/vhdl/dictionary/run.py +++ b/vunit/vhdl/dictionary/run.py @@ -10,6 +10,8 @@ ROOT = Path(__file__).parent UI = VUnit.from_argv() +UI.add_vhdl_builtins() + UI.add_library("lib").add_source_files(ROOT / "test" / "*.vhd") UI.main() diff --git a/vunit/vhdl/logging/run.py b/vunit/vhdl/logging/run.py index d465c23a5..1ee0ad561 100644 --- a/vunit/vhdl/logging/run.py +++ b/vunit/vhdl/logging/run.py @@ -15,6 +15,7 @@ def main(): root = Path(__file__).parent ui = VUnit.from_argv() + ui.add_vhdl_builtins() vunit_lib = ui.library("vunit_lib") files = glob.glob(str(root / "test" / "*.vhd")) diff --git a/vunit/vhdl/path/run.py b/vunit/vhdl/path/run.py index 3472bf097..650acd46c 100644 --- a/vunit/vhdl/path/run.py +++ b/vunit/vhdl/path/run.py @@ -10,6 +10,8 @@ ROOT = Path(__file__).parent UI = VUnit.from_argv() +UI.add_vhdl_builtins() + UI.add_library("lib").add_source_files(ROOT / "test" / "*.vhd") UI.main() diff --git a/vunit/vhdl/random/run.py b/vunit/vhdl/random/run.py index 2381e2848..73ea8765d 100644 --- a/vunit/vhdl/random/run.py +++ b/vunit/vhdl/random/run.py @@ -10,7 +10,9 @@ ROOT = Path(__file__).parent UI = VUnit.from_argv() +UI.add_vhdl_builtins() UI.add_random() + UI.library("vunit_lib").add_source_files(ROOT / "test" / "*.vhd") UI.main() diff --git a/vunit/vhdl/run/run.py b/vunit/vhdl/run/run.py index 7617b3818..4396169ff 100644 --- a/vunit/vhdl/run/run.py +++ b/vunit/vhdl/run/run.py @@ -10,6 +10,8 @@ ROOT = Path(__file__).parent UI = VUnit.from_argv() +UI.add_vhdl_builtins() + UI.add_library("tb_run_lib").add_source_files(ROOT / "test" / "*.vhd") UI.main() diff --git a/vunit/vhdl/string_ops/run.py b/vunit/vhdl/string_ops/run.py index 3472bf097..650acd46c 100644 --- a/vunit/vhdl/string_ops/run.py +++ b/vunit/vhdl/string_ops/run.py @@ -10,6 +10,8 @@ ROOT = Path(__file__).parent UI = VUnit.from_argv() +UI.add_vhdl_builtins() + UI.add_library("lib").add_source_files(ROOT / "test" / "*.vhd") UI.main() diff --git a/vunit/vhdl/verification_components/run.py b/vunit/vhdl/verification_components/run.py index 2a3a4583a..bb1409d8c 100644 --- a/vunit/vhdl/verification_components/run.py +++ b/vunit/vhdl/verification_components/run.py @@ -11,8 +11,10 @@ ROOT = Path(__file__).parent UI = VUnit.from_argv() +UI.add_vhdl_builtins() UI.add_random() UI.add_verification_components() + LIB = UI.library("vunit_lib") LIB.add_source_files(ROOT / "test" / "*.vhd") From 0d6e38856a8578168c11449fd2a8d2729aaca932 Mon Sep 17 00:00:00 2001 From: umarcor Date: Tue, 9 Nov 2021 14:28:45 +0100 Subject: [PATCH 3/7] ui: make the builtins deprecation note more visible --- vunit/ui/__init__.py | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/vunit/ui/__init__.py b/vunit/ui/__init__.py index b930b5270..613d87b5e 100644 --- a/vunit/ui/__init__.py +++ b/vunit/ui/__init__.py @@ -161,17 +161,25 @@ def test_filter(name, attribute_names): self._test_bench_list = TestBenchList(database=database) self._builtins = Builtins(self, self._vhdl_standard, simulator_class) - if compile_builtins: - self.add_vhdl_builtins() - hline = "=" * 75 - print(hline) - LOGGER.warning( - """As of VUnit v5, option ``compile_builtins`` of methods 'from_args' and 'from_argv' is removed. -HDL builtins need to be added explicitly. -See https://github.com/VUnit/vunit/issues/777. -""" - ) - print(hline) + + self._printer.write( + """\ +Important! + +As of VUnit v5, HDL builtins are not compiled by default. +To preserve the functionality, the run script is now required to explicitly use +methods add_vhdl_builtins or add_verilog_builtins. + +Solution: + +prj = VUnit.from_argv() +prj.add_vhdl_builtins() # <- Add this line! + +See https://github.com/VUnit/vunit/issues/777 and http://vunit.github.io/vhdl_libraries.html. + +""", + fg="bi", + ) def _create_database(self): """ From 19af7a0034209837f0e743d98e038aaa29087514 Mon Sep 17 00:00:00 2001 From: umarcor Date: Tue, 9 Nov 2021 15:24:34 +0100 Subject: [PATCH 4/7] docs: rename 'VHDL Libraries' to 'HDL Libraries' --- docs/about.rst | 4 ++-- docs/{vhdl_libraries.rst => hdl_libraries.rst} | 2 +- docs/index.rst | 2 +- vunit/ui/__init__.py | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) rename docs/{vhdl_libraries.rst => hdl_libraries.rst} (91%) diff --git a/docs/about.rst b/docs/about.rst index ce5d7e0d4..697f7edef 100644 --- a/docs/about.rst +++ b/docs/about.rst @@ -42,7 +42,7 @@ Main Features * Outputs JUnit report files for better `Jenkins`_ :ref:`integration `. * Builds on the commonly used `xUnit`_ architecture. -* :ref:`Built-in VHDL utility libraries `: +* :ref:`Built-in HDL utility libraries `: * :doc:`Run library <./run/user_guide>` providing functionality for declaring multiple test cases within HDL testbenches. @@ -84,7 +84,7 @@ Those are made available through the built-ins API, which is based on the librar Both the core and builtins are available in the public :ref:`python_interface` of VUnit. Details about how to execute a project are explained in :ref:`cli`. -Further info about the optional libraries is found in :ref:`vhdl_libraries`. +Further info about the optional libraries is found in :ref:`hdl_libraries`. Experimental co-simulation through GHDL's VHPIDIRECT is supported in `VUnit/cosim `__. diff --git a/docs/vhdl_libraries.rst b/docs/hdl_libraries.rst similarity index 91% rename from docs/vhdl_libraries.rst rename to docs/hdl_libraries.rst index 2b546b43a..a81f7c00f 100644 --- a/docs/vhdl_libraries.rst +++ b/docs/hdl_libraries.rst @@ -1,4 +1,4 @@ -.. _vhdl_libraries: +.. _hdl_libraries: VHDL Libraries ============== diff --git a/docs/index.rst b/docs/index.rst index 956acd86f..d621025d8 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -35,7 +35,7 @@ often"* approach through automation. :ref:`Read more ` user_guide cli py/ui - vhdl_libraries + hdl_libraries examples .. toctree:: diff --git a/vunit/ui/__init__.py b/vunit/ui/__init__.py index 613d87b5e..955336974 100644 --- a/vunit/ui/__init__.py +++ b/vunit/ui/__init__.py @@ -175,7 +175,7 @@ def test_filter(name, attribute_names): prj = VUnit.from_argv() prj.add_vhdl_builtins() # <- Add this line! -See https://github.com/VUnit/vunit/issues/777 and http://vunit.github.io/vhdl_libraries.html. +See https://github.com/VUnit/vunit/issues/777 and http://vunit.github.io/hdl_libraries.html. """, fg="bi", From 7c6d19a0a9a2494ed2ad2a3f78ad8605f127811e Mon Sep 17 00:00:00 2001 From: umarcor Date: Wed, 10 Nov 2021 18:33:54 +0100 Subject: [PATCH 5/7] builtins: move the warning from 'builtins' to 'project', get script code from '__main__' --- vunit/project.py | 68 ++++++++++++++++++++++++++++++++++++++++---- vunit/ui/__init__.py | 19 ------------- 2 files changed, 63 insertions(+), 24 deletions(-) diff --git a/vunit/project.py b/vunit/project.py index 2c30385cf..6e5436016 100644 --- a/vunit/project.py +++ b/vunit/project.py @@ -168,7 +168,67 @@ def add_manual_dependency(self, source_file, depends_on): self._manual_dependencies.append((source_file, depends_on)) @staticmethod - def _find_primary_secondary_design_unit_dependencies(source_file): + def _failed_to_find_primary_design_unit_in_library(source_file_name, primary_design_unit, library_name): + """ + Show a warning about a primary unit not found in a library. + + Guess whether the error is produced because of missing builtins. + """ + LOGGER.warning( + "%s: failed to find a primary design unit '%s' in library '%s'", + source_file_name, + primary_design_unit, + library_name, + ) + # From there on, we try to guess whether the error is produced because of missing builtins. + if library_name != "vunit_lib": + # If the library is not VUnit's, we assume it's unrelated. + return + + # We get the main script (the one executed by the user), and we read all the content. + import __main__ # pylint: disable=import-outside-toplevel + + rscript = Path(__main__.__file__) + with rscript.open("r", encoding="utf-8") as fptr: + content = list(fptr) + + for line in content: + if "add_vhdl_builtins" in line: + # If the user is already aware of the feature, but it is commented/hidden, we assume it's known. + return + + # Find the line where 'from_args' or 'from_argv' are used. + for num, line in enumerate(content, 1): + if ".from_arg" in line: + # Print a block message telling the user which file and line to modify. + solution = f""" +Solution - Add a call to 'add_vhdl_builtins()' after the following location: + + File: {rscript!s} + Line: {num} + +As shown below: + +{num-1}| {content[num-2].rstrip()} +{num}| {line.rstrip()} +{num+1}|+ {line.split('=')[0].rstrip()}.add_vhdl_builtins() # Add this line! +{num+2}| {content[num].rstrip()} +{num+3}| {content[num+1].rstrip()} +""" + hline = "=" * 75 + print(hline) + LOGGER.critical( + """As of VUnit v5, HDL builtins are not compiled by default. +To preserve the functionality, the run script is now required to explicitly use +methods 'add_vhdl_builtins()' or 'add_verilog_builtins()'. +%s +See https://github.com/VUnit/vunit/issues/777 and http://vunit.github.io/hdl_libraries.html.""", + solution, + ) + print(hline) + break + + def _find_primary_secondary_design_unit_dependencies(self, source_file): """ Iterate over dependencies between the primary design units of the source_file and their secondary design units @@ -182,8 +242,7 @@ def _find_primary_secondary_design_unit_dependencies(source_file): try: primary_unit = library.primary_design_units[unit.primary_design_unit] except KeyError: - LOGGER.warning( - "%s: failed to find a primary design unit '%s' in library '%s'", + self._failed_to_find_primary_design_unit_in_library( source_file.name, unit.primary_design_unit, library.name, @@ -238,8 +297,7 @@ def _find_other_vhdl_design_unit_dependencies( # pylint: disable=too-many-branc primary_unit = library.primary_design_units[ref.design_unit] except KeyError: if not library.is_external: - LOGGER.warning( - "%s: failed to find a primary design unit '%s' in library '%s'", + self._failed_to_find_primary_design_unit_in_library( source_file.name, ref.design_unit, library.name, diff --git a/vunit/ui/__init__.py b/vunit/ui/__init__.py index 955336974..8bcc2e1cb 100644 --- a/vunit/ui/__init__.py +++ b/vunit/ui/__init__.py @@ -162,25 +162,6 @@ def test_filter(name, attribute_names): self._builtins = Builtins(self, self._vhdl_standard, simulator_class) - self._printer.write( - """\ -Important! - -As of VUnit v5, HDL builtins are not compiled by default. -To preserve the functionality, the run script is now required to explicitly use -methods add_vhdl_builtins or add_verilog_builtins. - -Solution: - -prj = VUnit.from_argv() -prj.add_vhdl_builtins() # <- Add this line! - -See https://github.com/VUnit/vunit/issues/777 and http://vunit.github.io/hdl_libraries.html. - -""", - fg="bi", - ) - def _create_database(self): """ Create a persistent database to store expensive parse results From 6698e011259a5b16bc50b5d302a349a02cd29c24 Mon Sep 17 00:00:00 2001 From: umarcor Date: Tue, 9 Nov 2021 15:47:17 +0100 Subject: [PATCH 6/7] docs: reorganise 'HDL Libraries', add section 'Guides' --- docs/blog/2018_02_12_vunit3.rst | 4 +- docs/check/user_guide.rst | 4 +- docs/com/user_guide.rst | 6 +- docs/conf.py | 1 + docs/data_types/user_guide.rst | 4 +- docs/examples.py | 1 + docs/hdl_libraries.rst | 95 ++++++++++++++++++--- docs/index.rst | 14 ++- docs/logging/user_guide.rst | 4 +- docs/release_notes/3.0.0.rst | 2 +- docs/run/user_guide.rst | 4 +- docs/verification_components/user_guide.rst | 12 +-- examples/vhdl/array_axis_vcs/run.py | 2 +- 13 files changed, 118 insertions(+), 35 deletions(-) diff --git a/docs/blog/2018_02_12_vunit3.rst b/docs/blog/2018_02_12_vunit3.rst index 99aa7f2b5..e716aed6c 100644 --- a/docs/blog/2018_02_12_vunit3.rst +++ b/docs/blog/2018_02_12_vunit3.rst @@ -75,7 +75,7 @@ Verification Components ----------------------- In VUnit 3.0 we have a *beta* version of a :ref:`verification -component ` library. Using the improved ``com`` message +component ` library. Using the improved ``com`` message passing it is very easy to create advanced verification components and we hope to get many pull requests from users for other bus types in the future. We've already seen some initiatives from the VUnit community @@ -93,7 +93,7 @@ Out of the box we provide the following verification components: - UART RX/TX - (B)RAM master -For more information see the :ref:`verification component library user guide `. +For more information see the :ref:`verification component library user guide `. Logging ------- diff --git a/docs/check/user_guide.rst b/docs/check/user_guide.rst index 6bcac19e8..ff0373c69 100644 --- a/docs/check/user_guide.rst +++ b/docs/check/user_guide.rst @@ -1,7 +1,7 @@ .. _check_library: -Check Library -============= +Check Library User Guide +======================== Introduction ------------ diff --git a/docs/com/user_guide.rst b/docs/com/user_guide.rst index cf18b7fd2..e4479dac5 100644 --- a/docs/com/user_guide.rst +++ b/docs/com/user_guide.rst @@ -1,8 +1,8 @@ .. _com_user_guide: -##################### -Communication Library -##################### +################################ +Communication Library User Guide +################################ ************ Introduction diff --git a/docs/conf.py b/docs/conf.py index 3a0bc5f56..708739b95 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -115,6 +115,7 @@ intersphinx_mapping = { "python": ("https://docs.python.org/3.8/", None), "pytest": ("https://docs.pytest.org/en/latest/", None), + "osvb": ("https://umarcor.github.io/osvb", None), } # -- ExtLinks ----------------------------------------------------------------- diff --git a/docs/data_types/user_guide.rst b/docs/data_types/user_guide.rst index 623618037..dfde471a7 100644 --- a/docs/data_types/user_guide.rst +++ b/docs/data_types/user_guide.rst @@ -1,7 +1,7 @@ .. _data_types_library: -Data Types -########## +Data Types User Guide +##################### VUnit comes with a number of convenient data types included: diff --git a/docs/examples.py b/docs/examples.py index 9b9425be6..cd7bf6dc6 100644 --- a/docs/examples.py +++ b/docs/examples.py @@ -71,6 +71,7 @@ def _get_eg_doc(location: Path, ref): title = eg_doc.split("---", 1)[0][0:-1] return "\n".join( [ + f".. _examples:{location.parent.name}:{location.name}:\n", title, "-" * len(title), f":vunit_example:`➚ examples/{ref} <{ref!s}>`\n", diff --git a/docs/hdl_libraries.rst b/docs/hdl_libraries.rst index a81f7c00f..6094a7562 100644 --- a/docs/hdl_libraries.rst +++ b/docs/hdl_libraries.rst @@ -1,15 +1,90 @@ .. _hdl_libraries: -VHDL Libraries +HDL Libraries +############# + +VHDL +==== + +Builtins +-------- + +By default, VUnit provides bare minimal functionality for running testbenches. +In practice, most users want to use HDL utilities to reduce verbosity and improve reporting when writting tests. +VUnit includes several optional libraries in a group named *VHDL builtins* (see :meth:`add_vhdl_builtins() `): + +* :vunit_file:`core ` +* :vunit_file:`logging ` (see :ref:`logging_library`) +* :vunit_file:`string_ops ` +* :vunit_file:`check ` (see :ref:`check_library`) +* :vunit_file:`dictionary ` +* :vunit_file:`run ` (see :ref:`run_library`) +* :vunit_file:`path ` + +Most of the utilities are based on some internal data types providing dynamic arrays and queues (FIFOs). +See :ref:`data_types_library`. + +Communication +------------- + +The VUnit communication library (``com``) provides a high-level communication mechanism based on the +`actor model `__. + +See :meth:`add_com() ` and :ref:`com_user_guide`. + +.. NOTE:: + The Communication Library depends on the builtins, which are added implicitly. + +Verification Components +----------------------- + +.. note:: This library is released as a *BETA* version. This means non-backwards compatible changes are still likely + based on feedback from our users. + +The VUnit Verification Component Library (VCL) contains a number of useful +:ref:`Verification Components ` (VC) as well as a set of utilities for writing your own +verification component. +Verification components allow a better overview in the test bench by raising the abstraction level of bus transactions. +Even if you do not need the advanced features that VCs offer you may still benefit from using peer-verified models of an +AXI-bus instead of re-implementing it yourself. + +See :meth:`add_verification_components() ` and :ref:`vc_user_guide`. + +.. NOTE:: + The VCL depends on both the Communication Library and OSVVM, which are added implicitly. + +Random +------ + +VUnit provides random integer vector and pointer generation, based on built-in :ref:`Data Types ` +and OSVVM. + +See :meth:`add_random() `. + +OSVVM +----- + +VUnit includes the core of `OSVVM `__ as a submodule and internal dependency of optional +libraries such as Random or Verification Components. +However, it can be added explicitly through :meth:`add_osvvm() `. + +Moreover, multiple approaches are supported for using `OSVVMLibraries `__ in +VUnit. +See :ref:`OSVB: Examples » SISO AXI4 Stream `. + +JSON-for-VHDL +------------- + +VUnit includes `JSON-for-VHDL `__ as a submodule. +JSON-for-VHDL is an alternative to composite top-level generics, which supports any depth in the content structure. + +See :meth:`add_json4vhdl() `, :vunit_file:`json4vhdl.py ` and example +:ref:`JSON-for-VHDL `. + +System Verilog ============== -.. toctree:: - :maxdepth: 1 +Builtins +-------- - id/user_guide - logging/user_guide - check/user_guide - run/user_guide - com/user_guide - data_types/user_guide - verification_components/user_guide +See :meth:`add_verilog_builtins() ` and :vunit_file:`vunit_pkg.sv `. diff --git a/docs/index.rst b/docs/index.rst index d621025d8..063d1eb44 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -29,10 +29,22 @@ often"* approach through automation. :ref:`Read more ` testimonials/testimonials .. toctree:: - :caption: Documentation + :caption: Guides :hidden: user_guide + id/user_guide + logging/user_guide + check/user_guide + run/user_guide + com/user_guide + verification_components/user_guide + data_types/user_guide + +.. toctree:: + :caption: Reference + :hidden: + cli py/ui hdl_libraries diff --git a/docs/logging/user_guide.rst b/docs/logging/user_guide.rst index 62794d3f9..1fbecaaef 100644 --- a/docs/logging/user_guide.rst +++ b/docs/logging/user_guide.rst @@ -1,7 +1,7 @@ .. _logging_library: -Logging Library -=============== +Logging Library User Guide +========================== Introduction ------------ diff --git a/docs/release_notes/3.0.0.rst b/docs/release_notes/3.0.0.rst index afd32f007..1f58c21a0 100644 --- a/docs/release_notes/3.0.0.rst +++ b/docs/release_notes/3.0.0.rst @@ -1,4 +1,4 @@ -- *beta* version of a :ref:`verification component ` library. +- *beta* version of a :ref:`verification component ` library. - AXI read/write slaves - Memory model diff --git a/docs/run/user_guide.rst b/docs/run/user_guide.rst index 06627818d..2499b1cff 100644 --- a/docs/run/user_guide.rst +++ b/docs/run/user_guide.rst @@ -1,7 +1,7 @@ .. _run_library: -Run Library -=========== +Run Library User Guide +====================== Introduction ------------ diff --git a/docs/verification_components/user_guide.rst b/docs/verification_components/user_guide.rst index c2e5c3fb1..6ba1b35d1 100644 --- a/docs/verification_components/user_guide.rst +++ b/docs/verification_components/user_guide.rst @@ -1,18 +1,12 @@ -.. _vc_library: +.. _vc_user_guide: -Verification Component Library -=============================== +Verification Components User Guide +================================== .. NOTE:: This library is released as a *BETA* version. This means non-backwards compatible changes are still likely based on feedback from our users. -The VUnit Verification Component Library (VCL) contains a number of useful :ref:`Verification Components ` -(VC) as well as a set of utilities for writing your own verification component. -Verification components allow a better overview in the test bench by raising the abstraction level of bus transactions. -Even if you do not need the advanced features that VCs offer you may still benefit from using pre-verified models of an -AXI-bus instead of re-implementing it yourself. - Included verification components (VCs): - Avalon Memory-Mapped master diff --git a/examples/vhdl/array_axis_vcs/run.py b/examples/vhdl/array_axis_vcs/run.py index 19c7cb1e3..760fa784b 100644 --- a/examples/vhdl/array_axis_vcs/run.py +++ b/examples/vhdl/array_axis_vcs/run.py @@ -13,7 +13,7 @@ Shows how to use ``integer_array_t``, ``axi_stream_master_t`` and ``axi_stream_slave_t``. A CSV file is read, the content is sent in a row-major order to an AXI Stream buffer (FIFO) and it is received back to be saved in a different file. Further information can -be found in the :ref:`verification component library user guide `, +be found in the :ref:`verification component library user guide `, in subsection :ref:`Stream ` and in :vunit_file:`vhdl/verification_components/test/tb_axi_stream.vhd `. """ From f687a268c84b265e92d39fd2cbfbd068dea2bc06 Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Sun, 23 Apr 2023 23:07:56 +0100 Subject: [PATCH 7/7] docs/news: add fragments for #559, #764 and #777 --- docs/news.d/559.breaking.rst | 4 ++++ docs/news.d/764.breaking.rst | 4 ++++ docs/news.d/764.doc.rst | 1 + docs/news.d/777.breaking.rst | 4 ++++ 4 files changed, 13 insertions(+) create mode 100644 docs/news.d/559.breaking.rst create mode 100644 docs/news.d/764.breaking.rst create mode 100644 docs/news.d/764.doc.rst create mode 100644 docs/news.d/777.breaking.rst diff --git a/docs/news.d/559.breaking.rst b/docs/news.d/559.breaking.rst new file mode 100644 index 000000000..638655110 --- /dev/null +++ b/docs/news.d/559.breaking.rst @@ -0,0 +1,4 @@ +HDL builtins are not compiled by default. +To preserve the functionality, the run script is now required to explicitly use methods +:meth:`add_vhdl_builtins() ` or +:meth:`add_verilog_builtins() `. diff --git a/docs/news.d/764.breaking.rst b/docs/news.d/764.breaking.rst new file mode 100644 index 000000000..638655110 --- /dev/null +++ b/docs/news.d/764.breaking.rst @@ -0,0 +1,4 @@ +HDL builtins are not compiled by default. +To preserve the functionality, the run script is now required to explicitly use methods +:meth:`add_vhdl_builtins() ` or +:meth:`add_verilog_builtins() `. diff --git a/docs/news.d/764.doc.rst b/docs/news.d/764.doc.rst new file mode 100644 index 000000000..5f1c259f6 --- /dev/null +++ b/docs/news.d/764.doc.rst @@ -0,0 +1 @@ +Rename 'VHDL Libraries' to :ref:`hdl_libraries`. Add section :ref:`Guides `. diff --git a/docs/news.d/777.breaking.rst b/docs/news.d/777.breaking.rst new file mode 100644 index 000000000..638655110 --- /dev/null +++ b/docs/news.d/777.breaking.rst @@ -0,0 +1,4 @@ +HDL builtins are not compiled by default. +To preserve the functionality, the run script is now required to explicitly use methods +:meth:`add_vhdl_builtins() ` or +:meth:`add_verilog_builtins() `.