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Upstream VTR throws error on buffered switches #548
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acomodi
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VTR throws error on buffered switches
Upstream VTR throws error on buffered switches
Sep 22, 2020
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With master+wip and master getting closer, there is one outstanding fix to be done to have an error-free build of Symbyflow tests with upstream VTR.
The error encountered is due to the following code block:
vtr-verilog-to-routing/vpr/src/route/rr_graph_indexed_data.cpp
Lines 369 to 394 in b22e1fe
In particular, VTR throws a fatal error as switches belonging to the same wire segment have different
buffered
values. This does not happen in the current master+wip, and the code block resposible looks like the following:vtr-verilog-to-routing/vpr/src/route/rr_graph_indexed_data.cpp
Lines 376 to 414 in f1a3bcc
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