diff --git a/src/main/scala/vexiiriscv/soc/litex/Soc.scala b/src/main/scala/vexiiriscv/soc/litex/Soc.scala
index 2829480a..1c7b3b0d 100644
--- a/src/main/scala/vexiiriscv/soc/litex/Soc.scala
+++ b/src/main/scala/vexiiriscv/soc/litex/Soc.scala
@@ -306,6 +306,12 @@ class Soc(c : SocConfig) extends Component {
       ))
       if (c.withDma) Axi4SpecRenamer(dma.bus)
 
+      if(withCoherency && withL2){
+        for (bank <- splited.wc.l2.cache.logic.cache.cache.data.banks) {
+          bank.ram.preventAsBlackBox() // Some synthesis tools have issues inferring efficient layout when byte mask is used.
+        }
+      }
+
 
       println(MemoryConnection.getMemoryTransfers(vexiis(0).dBus))