From a44cd59e836033a549ffcef232011e655a55f870 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 3 Oct 2024 14:53:25 +0200 Subject: [PATCH] sync --- ext/NaxSoftware | 2 +- ext/SpinalHDL | 2 +- src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ext/NaxSoftware b/ext/NaxSoftware index 3c613a25..d9d435ca 160000 --- a/ext/NaxSoftware +++ b/ext/NaxSoftware @@ -1 +1 @@ -Subproject commit 3c613a25f7f6450ad1f7763c173c45b4a97ddf21 +Subproject commit d9d435cacc1926aa285aaf0eed5ba84d6238201b diff --git a/ext/SpinalHDL b/ext/SpinalHDL index 6293c5dc..949a5b72 160000 --- a/ext/SpinalHDL +++ b/ext/SpinalHDL @@ -1 +1 @@ -Subproject commit 6293c5dc7f9fb4ef778346301a51bb0c2fce5004 +Subproject commit 949a5b72d1df2771e22bcf4bb9d374f16a384e7f diff --git a/src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala b/src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala index 95462650..9742b82c 100644 --- a/src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala +++ b/src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala @@ -59,7 +59,7 @@ class TilelinkVexiiRiscvFiber(plugins : ArrayBuffer[Hostable]) extends Area with val up = clint.createPort(pp.hartIds(0)) priv.mti << up.mti priv.msi << up.msi - DataCc(up.stoptime, priv.stoptime.clockDomain(RegNext(priv.stoptime))) + DataCc(up.stoptime, priv.stoptime.clockDomain(RegNext(priv.stoptime)), initValue = U(0, 64 bits)) val time = priv.plugin.p.withRdTime generate new Area{ val timeBuffer = priv.rdtime.clockDomain(Reg(UInt(64 bits))) DataCc(timeBuffer, clint.time)