From 91cc12700109e99e4056ca4693fbe2611484e8eb Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 23 Sep 2024 18:37:26 +0200 Subject: [PATCH] sync --- src/main/scala/vexiiriscv/Param.scala | 4 ++-- src/main/scala/vexiiriscv/soc/litex/Soc.scala | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala index e4a4b8a..90053ff 100644 --- a/src/main/scala/vexiiriscv/Param.scala +++ b/src/main/scala/vexiiriscv/Param.scala @@ -262,8 +262,8 @@ class ParamSimple(){ privParam.withDebug = true -// privParam.debugTriggers = 4 -// privParam.debugTriggersLsu = true + privParam.debugTriggers = 4 + privParam.debugTriggersLsu = true embeddedJtagTap = true diff --git a/src/main/scala/vexiiriscv/soc/litex/Soc.scala b/src/main/scala/vexiiriscv/soc/litex/Soc.scala index 3a82dc5..3e4ff0a 100644 --- a/src/main/scala/vexiiriscv/soc/litex/Soc.scala +++ b/src/main/scala/vexiiriscv/soc/litex/Soc.scala @@ -462,6 +462,8 @@ object SocGen extends App{ // val from = cpu0.reflectBaseType("LsuL1Plugin_logic_c_pip_ctrl_2_up_onPreCtrl_HIT_DIRTY") //That big // val to = cpu0.reflectBaseType("PrivilegedPlugin_logic_harts_0_debug_dcsr_stepLogic_stepped") +// val from = cpu0.reflectBaseType("early0_SrcPlugin_logic_addsub_combined_rs2Patched") //That big +// val to = cpu0.reflectBaseType("toplevel_execute_ctrl2_up_early0_SrcPlugin_SRC2_lane0") // val drivers = mutable.LinkedHashSet[BaseType]()