From 194adb442abffd196a9ff5e97059563e2c5fc82b Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Fri, 20 Sep 2024 23:41:59 +0200
Subject: [PATCH] #26 fix GenerateTilelink mem bus data width

---
 src/main/scala/vexiiriscv/Generate.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/vexiiriscv/Generate.scala b/src/main/scala/vexiiriscv/Generate.scala
index 52014ce..2dd4614 100644
--- a/src/main/scala/vexiiriscv/Generate.scala
+++ b/src/main/scala/vexiiriscv/Generate.scala
@@ -65,7 +65,7 @@ object GenerateTilelink extends App {
       val mem = new SlaveBus(
         M2sSupport(
           transfers = M2sTransfers.all,
-          dataWidth = param.xlen,
+          dataWidth = param.memDataWidth,
           addressWidth = param.physicalWidth
         ),
         S2mParameters(