diff --git a/source/VexiiRiscv/Introduction/index.rst b/source/VexiiRiscv/Introduction/index.rst
index 07c234c..fdcb312 100644
--- a/source/VexiiRiscv/Introduction/index.rst
+++ b/source/VexiiRiscv/Introduction/index.rst
@@ -16,7 +16,7 @@ VexiiRiscv is a from scratch second iteration of VexRiscv, with the following go
 - Proper branch prediction
 - ...
 
-On this date (22/01/2024) the status is : 
+On this date (08/03/2024) the status is : 
 
 - rv 32/64 imacsu supported 
 - Can run baremetal benchmarks (2.50 dhrystone/mhz, 5.24 coremark/mhz)
@@ -25,6 +25,7 @@ On this date (22/01/2024) the status is :
 - BTB/RAS/GShare branch prediction supported
 - MMU SV32/SV39 supported
 - can run linux/buildroot in simulation
+- LSU store buffer supported
 
 Here is a diagram with 2 issue / early+late alu / 6 stages configuration (note that the pipeline structure can vary a lot):
 
@@ -50,3 +51,18 @@ Here is a list of important assumptions and things to know about :
 - trap/flush/pc request from the pipeline, once asserted one cycle can not be undone. This also mean that while a given instruction is stuck somewere, if that instruction did raised on of those request, nothing should change the execution path. For instance, a sudden cache line refill completion should not lift the request from the LSU asking a redo (due to cache refill hazard).
 - In the execute pipeline, stage.up(RS1/RS2) is the value to be used, while stage.down(RS1/RS2) should not be used, as it implement the bypassing for the next stage
 - Fetch.ctrl(0) isn't persistant.
+
+About VexRiscv (not VexiiRiscv)
+------------------------------------
+
+There is few reasons why VexiiRiscv exists instead of doing incremental upgrade on VexRiscv
+
+- Mostly, all the VexRiscv parts could be subject for upgrades
+- VexRiscv frontend / branch prediction is quite messy
+- The whole VexRiscv pipeline would have need a complete overhaul in oder to support multiple issue / late-alu
+- The VexRiscv plugin system has hits some limits
+- VexRiscv accumulated quite a bit of technical debt over time (2017)
+- The VexRiscv data cache being write though start to create issues the faster the frequency goes (DRAM can't follow)
+- The VexRiscv verification infrastructure based on its own golden model isn't great.
+
+So, enough is enough, it was time to start fresh :D