-
Notifications
You must be signed in to change notification settings - Fork 40
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
blackboxAndClock #32
Comments
SpinalConfig.dumpWave(0, "./mem.vcd") is about how the verilog is generated, but it doesn't interract with SpinalSim i would say, i'm not sure verilator use the verilog to figure out how to trace things. You need to do SimConfig.withWave.... instead
Not implemented so far, it juste trace everything |
I want to dump rtl top scope(MemorySumming) wave data for better debug with rtl verilog |
I tried : SimConfig.withWave.compile(new Component{
val x = slave Stream(UInt(8 bits))
val y = master Stream(UInt(8 bits))
x.queue(4) >> y // the queue function create a fifo module
}).doSim{dut =>
sleep(10)
} It gives me full visibility :
Isn't it what you want ? (all modules being in the wave |
Thanks for your try. But this is not my want.What the vcd file of my want is only include rtl and not include
Because the spinalhdl not generate verilog include Top module. |
Ahhh i see. Hmm i don't know then, not sure if Verilator can be configured for this. The only workaround i know (in terms of flow) is to use GTKwave to look at the wave. Also instead of "withWave", to use "withFstWave" that produce a compresed waveform which is much better to use. But all of this may not fit your use case. |
Q1:
when i point the dump depth with verilator
and no waves generated.
The sim reports as follow:
Q2:
how to point the dump depth with hier?
The second var in dumpvar().
The text was updated successfully, but these errors were encountered: