From e77465cd41aa60fe35bad4c365a0aaeca21c32db Mon Sep 17 00:00:00 2001 From: chengguanghui Date: Mon, 30 Sep 2024 10:19:08 +0800 Subject: [PATCH 1/3] fix(CSR): remove reg in `scountovf`. --- .../xiangshan/backend/fu/NewCSR/SupervisorLevel.scala | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala index a5ee6dfd23..b5ce5f545b 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala @@ -154,13 +154,11 @@ trait SupervisorLevel { self: NewCSR with MachineLevel => override val len: Int = 32 val OFVEC = RO(31, 3).withReset(0.U) }) with HasMhpmeventOfBundle { - reg.OFVEC := ofVec regOut.OFVEC := Mux1H(Seq( - privState.isModeM -> reg.OFVEC.asUInt, - privState.isModeHS -> (mcounteren.HPM.asUInt & reg.OFVEC.asUInt), - privState.isModeVS -> (mcounteren.HPM.asUInt & hcounteren.HPM.asUInt & reg.OFVEC.asUInt), - ) - ) + privState.isModeM -> ofVec, + privState.isModeHS -> (mcounteren.HPM.asUInt & ofVec), + privState.isModeVS -> (mcounteren.HPM.asUInt & hcounteren.HPM.asUInt & ofVec), + )) }).setAddr(CSRs.scountovf) val sstateen0 = Module(new CSRModule("Sstateen", new SstateenBundle0) with HasStateen0Bundle { From d08a73ceadc87b739f5d96696aaf608e7521082b Mon Sep 17 00:00:00 2001 From: chengguanghui Date: Wed, 9 Oct 2024 15:40:57 +0800 Subject: [PATCH 2/3] fix(mhpmevent): add MhpmeventBundle for mhpmevent csr. --- .../backend/fu/NewCSR/MachineLevel.scala | 63 +++++++++++-------- .../xiangshan/backend/fu/NewCSR/NewCSR.scala | 35 +++++++---- 2 files changed, 60 insertions(+), 38 deletions(-) diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala index 72bde5b7d1..b82f9bc4e1 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala @@ -14,7 +14,7 @@ import xiangshan.backend.fu.NewCSR.CSREnumTypeImplicitCast._ import xiangshan.backend.fu.NewCSR.ChiselRecordForField._ import xiangshan.backend.fu.PerfCounterIO import xiangshan.backend.fu.NewCSR.CSRConfig._ -import xiangshan.backend.fu.NewCSR.CSRFunc.wNoEffectWhen +import xiangshan.backend.fu.NewCSR.CSRFunc._ import scala.collection.immutable.SeqMap @@ -165,8 +165,12 @@ trait MachineLevel { self: NewCSR => .setAddr(CSRs.mcountinhibit) val mhpmevents: Seq[CSRModule[_]] = (3 to 0x1F).map(num => - Module(new CSRModule(s"Mhpmevent$num") with HasPerfEventBundle { - regOut := this.perfEvents(num - 3) + Module(new CSRModule(s"Mhpmevent$num", new MhpmeventBundle) with HasOfFromPerfCntBundle { + when(wen){ + reg.OF := wdata.OF + }.elsewhen(ofFromPerfCnt) { + reg.OF := ofFromPerfCnt + } }) .setAddr(CSRs.mhpmevent3 - 3 + num) ) @@ -418,20 +422,6 @@ trait MachineLevel { self: NewCSR => machineLevelCSRMods.map(csr => (csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt)).iterator ) - // read/write/update mhpmevents -> read/write/update perfEvents - val perfEvents = List.fill(8)(RegInit("h0000000000".U(XLEN.W))) ++ - List.fill(8)(RegInit("h4010040100".U(XLEN.W))) ++ - List.fill(8)(RegInit("h8020080200".U(XLEN.W))) ++ - List.fill(5)(RegInit("hc0300c0300".U(XLEN.W))) - - mhpmevents.foreach { mod => - mod match { - case m: HasPerfEventBundle => - m.perfEvents := perfEvents - case _ => - } - } - } class MstatusBundle extends CSRBundle { @@ -630,16 +620,6 @@ class Mtval2Bundle extends FieldInitBundle class MhpmcounterBundle extends FieldInitBundle -// todo: for the future, delete bypass between mhpmevents and perfEvents -class MhpmeventBundle extends CSRBundle { - val OF = RW(63).withReset(0.U) - val MINH = RW(62).withReset(0.U) - val SINH = RW(61).withReset(0.U) - val UINH = RW(60).withReset(0.U) - val VSINH = RW(59).withReset(0.U) - val VUINH = RW(58).withReset(0.U) -} - class MEnvCfg extends EnvCfg { if (CSRConfig.EXT_SSTC) { this.STCE.setRW().withReset(1.U) @@ -684,6 +664,35 @@ class MipToMvip extends IpValidBundle { this.SEIP.bits.setRW() } +class MhpmeventBundle extends CSRBundle { + val OF = RW(63).withReset(0.U) + val MINH = RW(62).withReset(0.U) + val SINH = RW(61).withReset(0.U) + val UINH = RW(60).withReset(0.U) + val VSINH = RW(59).withReset(0.U) + val VUINH = RW(58).withReset(0.U) + val OPTYPE2 = OPTYPE(54, 50, wNoFilter).withReset(OPTYPE.OR) + val OPTYPE1 = OPTYPE(49, 45, wNoFilter).withReset(OPTYPE.OR) + val OPTYPE0 = OPTYPE(44, 40, wNoFilter).withReset(OPTYPE.OR) + val EVENT3 = RW(39, 30).withReset(0.U) + val EVENT2 = RW(29, 20).withReset(0.U) + val EVENT1 = RW(19, 10).withReset(0.U) + val EVENT0 = RW(9, 0).withReset(0.U) +} + +object OPTYPE extends CSREnum with WARLApply { + val OR = Value(0.U) + val AND = Value(1.U) + val XOR = Value(2.U) + val ADD = Value(4.U) + + override def isLegal(enumeration: CSREnumType): Bool = enumeration.isOneOf(OR, AND, XOR, ADD) +} + +trait HasOfFromPerfCntBundle { self: CSRModule[_] => + val ofFromPerfCnt = IO(Input(Bool())) +} + trait HasMipToAlias { self: CSRModule[_] => val mipAlias = Output(new MipBundle) } diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala index 533e97d548..e5965f2842 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala @@ -652,7 +652,11 @@ class NewCSR(implicit val p: Parameters) extends Module } mod match { case m: HasMhpmeventOfBundle => - m.ofVec := VecInit(mhpmevents.map(event => event.rdata.head(1).asBool)).asUInt //todo：fix + m.ofVec := VecInit(mhpmevents.map{ event => + val mhpmevent = Wire(new MhpmeventBundle) + mhpmevent := event.rdata + mhpmevent.OF.asBool + }).asUInt m.privState := privState m.mcounteren := mcounteren.rdata m.hcounteren := hcounteren.rdata @@ -1077,8 +1081,7 @@ class NewCSR(implicit val p: Parameters) extends Module * perf_begin * perf number: 29 (frontend 8, ctrlblock 8, memblock 8, huancun 5) */ - // tmp: mhpmevents is wrapper of perfEvents, read/write/update mhpmevents -> read/write/update perfEvents - val csrevents = perfEvents.slice(24, 29) + val csrevents = mhpmevents.slice(24, 29).map(_.rdata) val hcEvents = Wire(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) for (i <- 0 until numPCntHc * coreParams.L2NBanks) { @@ -1086,19 +1089,15 @@ class NewCSR(implicit val p: Parameters) extends Module } val hpmHc = HPerfMonitor(csrevents, hcEvents) - - val privState1H = Cat(privState.isModeM, privState.isModeHS, privState.isModeHU, privState.isModeVS, privState.isModeVU) - val countingEn = RegInit(0.U.asTypeOf(Vec(perfCntNum, Bool()))) - for (i <-0 until perfCntNum) { - countingEn(i) := ((~mhpmevents(i).rdata(62, 58)).asUInt & privState1H).orR - } val allPerfEvents = io.perf.perfEventsFrontend ++ io.perf.perfEventsBackend ++ io.perf.perfEventsLsu ++ hpmHc.getPerf + val countingEn = RegInit(0.U.asTypeOf(Vec(perfCntNum, Bool()))) val ofFromPerfCntVec = Wire(Vec(perfCntNum, Bool())) val lcofiReqVec = Wire(Vec(perfCntNum, Bool())) + for(i <- 0 until perfCntNum) { mhpmcounters(i) match { case m: HasPerfCounterBundle => @@ -1107,8 +1106,22 @@ class NewCSR(implicit val p: Parameters) extends Module ofFromPerfCntVec(i) := m.toMhpmeventOF case _ => } - perfEvents(i) := Mux(mhpmevents(i).w.wen, wdata, (perfEvents(i).head(1).asBool || ofFromPerfCntVec(i)) ## perfEvents(i).tail(1)) - lcofiReqVec(i) := ofFromPerfCntVec(i) && !mhpmevents(i).rdata.head(1) + + mhpmevents(i) match { + case m: HasOfFromPerfCntBundle => + m.ofFromPerfCnt := ofFromPerfCntVec(i) + case _ => + } + + val mhpmevent = Wire(new MhpmeventBundle) + mhpmevent := mhpmevents(i).rdata + lcofiReqVec(i) := ofFromPerfCntVec(i) && !mhpmevent.OF.asBool + + countingEn(i) := (privState.isModeM && !mhpmevent.MINH) || + (privState.isModeHS && !mhpmevent.SINH) || + (privState.isModeHU && !mhpmevent.UINH) || + (privState.isModeVS && !mhpmevent.VSINH) || + (privState.isModeVU && !mhpmevent.VUINH) } val lcofiReq = lcofiReqVec.asUInt.orR From 3572df91d951152744ba10a85a1184ee5eb8a6fd Mon Sep 17 00:00:00 2001 From: sinceforYy <1017657683@qq.com> Date: Thu, 10 Oct 2024 15:27:41 +0800 Subject: [PATCH 3/3] fix(csr): add difftest of mhpmevent overflow to diff csr mhpmeventn * Count overflow only from hardware incrementes of counter registers * Through XiangShan->difftest->NEMU, to make NEMU get mhpmevent.of --- src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala index e5965f2842..0af08e94ba 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala @@ -810,7 +810,6 @@ class NewCSR(implicit val p: Parameters) extends Module // perf val addrInPerfCnt = (wenLegal || ren) && ( (addr >= CSRs.mcycle.U) && (addr <= CSRs.mhpmcounter31.U) || - (addr === mcountinhibit.addr.U) || (addr >= CSRs.cycle.U) && (addr <= CSRs.hpmcounter31.U) || Cat(aiaSkipCSRs.map(_.addr.U === addr)).orR ) @@ -1444,6 +1443,13 @@ class NewCSR(implicit val p: Parameters) extends Module diffNonRegInterruptPendingEvent.platformIRPVstip := sstcIRGen.o.VSTIP diffNonRegInterruptPendingEvent.localCounterOverflowInterruptReq := mip.regOut.LCOFIP.asBool + val diffMhpmeventOverflowEvent = DifftestModule(new DiffMhpmeventOverflowEvent) + diffMhpmeventOverflowEvent.coreid := hartId + diffMhpmeventOverflowEvent.valid := Cat(mhpmevents.zipWithIndex.map{ case (event, i) => + !ofFromPerfCntVec(i) && RegNext(ofFromPerfCntVec(i)) || ofFromPerfCntVec(i) && !RegNext(ofFromPerfCntVec(i)) + }).orR + diffMhpmeventOverflowEvent.mhpmeventOverflow := VecInit(mhpmevents.map(_.regOut.asInstanceOf[MhpmeventBundle].OF.asBool)).asUInt + } }