Package the IP and compile it into a Verilog module

[han-jianing]

Before start

• I have read the RISC-V ISA Manual. 我已经阅读过 RISC-V 指令集手册。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the feature you'd like

能不能把香山的核封装成一个IP？把中断，AXI，JTAG暴露出来，编译成一个verilog的模块呢？

[TRANSLATION]
Can Xiangshan's core be encapsulated as an IP? What about exposing interrupts, AXI, JTAG and compiling them into a verilog module?

Additional context

No response

[Ma-YX]

感谢您的提问。如果您需要香山核的verilog代码，可以在XiangShan文件夹下执行make verilog命令，可以在build文件夹查看对应verilog代码。
欢迎您进行尝试，在尝试过程中如有具体问题，欢迎继续提问，共同探讨。

Thank you for your question. If you need the Verilog code, you can run the make verilog command in the XiangShan folder, and verilog code is in build folder. You are welcome to try it, and if you encounter any specific issues during the process, feel free to ask further questions, and we can explore them together.

[cebarobot]

目前，香山核本身就是包装为 XSTile 模块来集成进各种 SoC 系统的，您可以在生成后的 Verilog 中找到 XSTile 模块，并参照我们仿真用 SoC 模型的集成方式进行继承。

Currently, XiangShan Core is packaged into module XSTile to Integrate into other SoC systems. You could find the XSTile.sv in the generated Verilog files and follow the SimTop to integrate it.